{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T03:27:51Z","timestamp":1764732471793,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,12,3]],"date-time":"2011-12-03T00:00:00Z","timestamp":1322870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS 1116684"],"award-info":[{"award-number":["CNS 1116684"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,12,3]]},"DOI":"10.1145\/2155620.2155659","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T13:18:26Z","timestamp":1331039906000},"page":"329-338","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":165,"title":["Multi retention level STT-RAM cache designs with a dynamic refresh scheme"],"prefix":"10.1145","author":[{"given":"Zhenyu","family":"Sun","sequence":"first","affiliation":[{"name":"Polytechnic Institute of New York University, Metrotech Center, Brooklyn, NY"}]},{"given":"Xiuyuan","family":"Bi","sequence":"additional","affiliation":[{"name":"Polytechnic Institute of New York University, Metrotech Center, Brooklyn, NY"}]},{"given":"Hai (Helen)","family":"Li","sequence":"additional","affiliation":[{"name":"Polytechnic Institute of New York University, Metrotech Center, Brooklyn, NY"}]},{"given":"Weng-Fai","family":"Wong","sequence":"additional","affiliation":[{"name":"National University of Singapore, Computing Drive, Singapore"}]},{"given":"Zhong-Liang","family":"Ong","sequence":"additional","affiliation":[{"name":"National University of Singapore, Computing Drive, Singapore"}]},{"given":"Xiaochun","family":"Zhu","sequence":"additional","affiliation":[{"name":"Qualcomm Incorporated, Morehouse Drive, San Diego"}]},{"given":"Wenqing","family":"Wu","sequence":"additional","affiliation":[{"name":"Qualcomm Incorporated, Morehouse Drive, San Diego"}]}],"member":"320","published-online":{"date-parts":[[2011,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"http:\/\/www.rioshering.com\/nvsimwiki\/index.php.  http:\/\/www.rioshering.com\/nvsimwiki\/index.php."},{"key":"e_1_3_2_1_2_1","unstructured":"CACTI. http:\/\/www.hpl.hp.com\/research\/cacti\/.  CACTI. http:\/\/www.hpl.hp.com\/research\/cacti\/."},{"key":"e_1_3_2_1_3_1","first-page":"201","volume-title":"IEEE Custom Integrated Ckt. Conf.","author":"Cao Y.","year":"2000"},{"key":"e_1_3_2_1_4_1","unstructured":"R. Desikan and et. al. On-chip MRAM as a high-bandwidth low-latency replacement for DRAM physical memories. http:\/\/www.cs.utexas.edu\/ftp\/pub\/techreports\/tr02-47.pdf.  R. Desikan and et. al. On-chip MRAM as a high-bandwidth low-latency replacement for DRAM physical memories. http:\/\/www.cs.utexas.edu\/ftp\/pub\/techreports\/tr02-47.pdf."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391610"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509633.1509700"},{"key":"e_1_3_2_1_8_1","first-page":"459","volume-title":"IEEE IEDM","author":"Hosomi M.","year":"2005"},{"key":"e_1_3_2_1_9_1","unstructured":"Intel Core2 Quad Processor Q8200. http:\/\/ark.intel.com\/Product.aspx?id=36547.  Intel Core2 Quad Processor Q8200. http:\/\/ark.intel.com\/Product.aspx?id=36547."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.909751"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.842903"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2007.4488788"},{"volume-title":"Massachusetts Institute of Technology","year":"2007","author":"Loh L. Y.","key":"e_1_3_2_1_13_1"},{"key":"e_1_3_2_1_14_1","unstructured":"Marss86. http:\/\/www.marss86.org\/.  Marss86. http:\/\/www.marss86.org\/."},{"first-page":"761","volume-title":"Midwest Symp. on Circuits and Systems","author":"Nair P.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","first-page":"1","volume-title":"IEEE Int. Electron Devices Meeting","author":"Raychowdhury A.","year":"2009"},{"volume-title":"Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches. Proc. of 2011 HPCA","year":"2011","author":"Smullen C.","key":"e_1_3_2_1_17_1"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.62.570"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2008.2002386"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2008.2002386"},{"key":"e_1_3_2_1_22_1","first-page":"737","volume-title":"Proc. of DATE","author":"Wu X.","year":"2009"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2035509"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3556784"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"}],"event":{"name":"MICRO-44: The 44th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["IEEE","ACM Association for Computing Machinery","UFRGS Universidade Federal do Rio Grande do Sul","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS Computer Society"],"location":"Porto Alegre Brazil","acronym":"MICRO-44"},"container-title":["Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155659","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2155620.2155659","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:59Z","timestamp":1750273679000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155659"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,3]]},"references-count":25,"alternative-id":["10.1145\/2155620.2155659","10.1145\/2155620"],"URL":"https:\/\/doi.org\/10.1145\/2155620.2155659","relation":{},"subject":[],"published":{"date-parts":[[2011,12,3]]},"assertion":[{"value":"2011-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}