{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:11:51Z","timestamp":1774800711185,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,3,3]],"date-time":"2012-03-03T00:00:00Z","timestamp":1330732800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001711","name":"Swiss National Science Foundation","doi-asserted-by":"publisher","award":["SNSF 200021-130048"],"award-info":[{"award-number":["SNSF 200021-130048"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,3,3]]},"DOI":"10.1145\/2159430.2159442","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T13:18:26Z","timestamp":1331039906000},"page":"101-109","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting"],"prefix":"10.1145","author":[{"given":"Shivani","family":"Raghav","sequence":"first","affiliation":[{"name":"ESL - \u00c9cole Polytechnique, F\u00e9d\u00e9rale de Lausanne, CH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrea","family":"Marongiu","sequence":"additional","affiliation":[{"name":"DEIS - University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Pinto","sequence":"additional","affiliation":[{"name":"DEIS - University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"ESL- \u00c9cole Polytechnique, F\u00e9d\u00e9rale de Lausanne, CH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martino","family":"Ruggiero","sequence":"additional","affiliation":[{"name":"ESL- \u00c9cole Polytechnique, F\u00e9d\u00e9rale de Lausanne, CH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"DEIS - University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM-GPU Hybrid Supercomputer. http:\/\/www.montblanc-project.eu\/.  ARM-GPU Hybrid Supercomputer. http:\/\/www.montblanc-project.eu\/."},{"key":"e_1_3_2_1_2_1","unstructured":"NVIDIA's Tegra System-on-Chip http:\/\/www.nvidia.com\/object\/tegra-2.html.  NVIDIA's Tegra System-on-Chip http:\/\/www.nvidia.com\/object\/tegra-2.html."},{"key":"e_1_3_2_1_3_1","unstructured":"OMAP processors. http:\/\/focus.ti.com.  OMAP processors. http:\/\/focus.ti.com."},{"key":"e_1_3_2_1_4_1","unstructured":"Plurality Software Emulator for Multi-Cores http:\/\/www.plurality.com.  Plurality Software Emulator for Multi-Cores http:\/\/www.plurality.com."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024785"},{"key":"e_1_3_2_1_6_1","unstructured":"Intel's Larrabee. http:\/\/software.intel.com\/en-us\/articles\/larrabee\/.  Intel's Larrabee. http:\/\/software.intel.com\/en-us\/articles\/larrabee\/."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434077"},{"key":"e_1_3_2_1_8_1","unstructured":"NVIDIA CUDA Best Practices Guide version 3.2. http:\/\/developer.download.nvidia.com.  NVIDIA CUDA Best Practices Guide version 3.2. http:\/\/developer.download.nvidia.com."},{"key":"e_1_3_2_1_9_1","volume-title":"v.2.3.1,Aug","author":"Programming Guide NVIDIA CUDA","year":"2009","unstructured":"NVIDIA CUDA Programming Guide , v.2.3.1,Aug . 2009 . http:\/\/developer.download.nvidia.com\/ NVIDIA CUDA Programming Guide, v.2.3.1,Aug. 2009. http:\/\/developer.download.nvidia.com\/"},{"key":"e_1_3_2_1_10_1","unstructured":"ARM Semihosting Interface. http:\/\/infocenter.arm.com\/  ARM Semihosting Interface. http:\/\/infocenter.arm.com\/"},{"key":"e_1_3_2_1_11_1","unstructured":"The open SystemC initiative. http:\/\/www.systemc.org.  The open SystemC initiative. http:\/\/www.systemc.org."},{"key":"e_1_3_2_1_12_1","unstructured":"The Open Virtual Platforms (OVP) portal. http:\/\/www.ovpworld.org\/.  The Open Virtual Platforms (OVP) portal. http:\/\/www.ovpworld.org\/."},{"key":"e_1_3_2_1_13_1","unstructured":"QEMU - Full System Processor Emulator http:\/\/wiki.qemu.org.  QEMU - Full System Processor Emulator http:\/\/wiki.qemu.org."},{"key":"e_1_3_2_1_14_1","unstructured":"QEMU SystemC project. http:\/\/greensocs.com\/en\/Projects\/QEMUSystemC.  QEMU SystemC project. http:\/\/greensocs.com\/en\/Projects\/QEMUSystemC."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1496909.1496921"},{"key":"e_1_3_2_1_16_1","volume-title":"USA","author":"Brewer E. A.","year":"1991","unstructured":"E. A. Brewer , C. N. Dellarocas , A. Colbrook , and W. E. Weihl . Proteus: A high-performance parallel-architecture simulator. Technical report, Cambridge, MA , USA , 1991 . E. A. Brewer, C. N. Dellarocas, A. Colbrook, and W. E. Weihl. Proteus: A high-performance parallel-architecture simulator. Technical report, Cambridge, MA, USA, 1991."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2005.41"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982915"},{"key":"e_1_3_2_1_19_1","volume-title":"Workshop on Modeling, Benchmarking and Simulation","author":"Kanaujia S.","year":"2006","unstructured":"S. Kanaujia , I. Papazian , J. Chamberlain , and J. Baxter . Fastmp: A multi-core simulation methodology . In Workshop on Modeling, Benchmarking and Simulation , 2006 . S. Kanaujia, I. Papazian, J. Chamberlain, and J. Baxter. Fastmp: A multi-core simulation methodology. In Workshop on Modeling, Benchmarking and Simulation, 2006."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.37"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2007.4374971"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/4434.895100"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCGrid.2011.64"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2010.5547092"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837390"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICIECS.2010.5678362"},{"key":"e_1_3_2_1_30_1","first-page":"1","volume-title":"IC Design Technology (ICICDT), 2011 IEEE International Conference on","author":"Yeh T.-C.","year":"2011","unstructured":"T.-C. Yeh , Z.-Y. Lin , and M.-C. Chiang . Enabling tlm-2. 0 interface on qemu and systemc-based virtual platform . In IC Design Technology (ICICDT), 2011 IEEE International Conference on , pages 1 -- 4 , may 2011 . T.-C. Yeh, Z.-Y. Lin, and M.-C. Chiang. Enabling tlm-2.0 interface on qemu and systemc-based virtual platform. In IC Design Technology (ICICDT), 2011 IEEE International Conference on, pages 1--4, may 2011."},{"key":"e_1_3_2_1_31_1","first-page":"78","volume-title":"Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International","author":"Zheng G.","year":"2004","unstructured":"G. Zheng , G. Kakulapati , and L. Kale . Bigsim: a parallel simulator for performance prediction of extremely large parallel machines . In Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International , page 78 , april 2004 . G. Zheng, G. Kakulapati, and L. Kale. Bigsim: a parallel simulator for performance prediction of extremely large parallel machines. In Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International, page 78, april 2004."}],"event":{"name":"GPGPU-5: The 5th Annual Workshop on General Purpose Processing with Graphics Processing Units","location":"London United Kingdom","acronym":"GPGPU-5","sponsor":["ACM Association for Computing Machinery"]},"container-title":["Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2159430.2159442","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2159430.2159442","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:59:58Z","timestamp":1750244398000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2159430.2159442"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3,3]]},"references-count":31,"alternative-id":["10.1145\/2159430.2159442","10.1145\/2159430"],"URL":"https:\/\/doi.org\/10.1145\/2159430.2159442","relation":{},"subject":[],"published":{"date-parts":[[2012,3,3]]},"assertion":[{"value":"2012-03-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}