{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:13:22Z","timestamp":1764332002541,"version":"3.41.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2008-TJ-1819"],"award-info":[{"award-number":["2008-TJ-1819"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2012,4]]},"abstract":"<jats:p>Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this article, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm based on simulated allocation (SAL), a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved solutions compared to a baseline algorithm reflecting prior work. To evaluate the SAL method, we compare its performance with the widely used simulated annealing (SA) method and show that SAL is much faster than SA for this application, while providing solutions of very similar quality. We then extend the approach from a single-path routing to a multipath routing scheme and explore the trade-off between power consumption and runtime for these two schemes. Finally, we study the impact of various factors on the network performance in 3D NoCs, including the TSV count and the number of 3D tiers. Our studies show that link power and delay can be significantly improved when moving from a 2D to a 3D implementation, but the improvement flattens out as the number of 3D tiers goes beyond a certain point.<\/jats:p>","DOI":"10.1145\/2159542.2159544","type":"journal-article","created":{"date-parts":[[2012,4,24]],"date-time":"2012-04-24T18:41:10Z","timestamp":1335292870000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Optimized 3D Network-on-Chip Design Using Simulated Allocation"],"prefix":"10.1145","volume":"17","author":[{"given":"Pingqiang","family":"Zhou","sequence":"first","affiliation":[{"name":"University of Minnesota"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ping-Hung","family":"Yuh","sequence":"additional","affiliation":[{"name":"National Taiwan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554447"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966758"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.79"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.26"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084857"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.84"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147058"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"e_1_2_1_13_1","volume-title":"-S","author":"Kahng A.","year":"2009","unstructured":"Kahng , A. , Samadi , K. , Li , B. , and Peh , L . -S . 2009 . ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the Design, Automation and Test in Europe . Kahng, A., Samadi, K., Li, B., and Peh, L.-S. 2009. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the Design, Automation and Test in Europe."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250680"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.18"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.149"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.9.3.383"},{"volume-title":"Proceedings of the International Conference on Nano-Networks. 1--5.","author":"Loi I.","key":"e_1_2_1_18_1","unstructured":"Loi , I. , Angiolini , F. , and Benini , L . 2007. Supporting vertical links for 3D networks-on-chip: Toward an automated design and analysis flow . In Proceedings of the International Conference on Nano-Networks. 1--5. Loi, I., Angiolini, F., and Benini, L. 2007. Supporting vertical links for 3D networks-on-chip: Toward an automated design and analysis flow. In Proceedings of the International Conference on Nano-Networks. 1--5."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2003.813040"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2007.79"},{"volume-title":"Proceedings of the Materials Research Society Symposium.","author":"Morrow P.","key":"e_1_2_1_21_1","unstructured":"Morrow , P. , Black , B. , Kobrinsky , M. J. , Muthukumar , S. , Nelson , D. , Park , C.-H. , and Webb , C . 2007. Design and fabrication of 3D microprocessors . In Proceedings of the Materials Research Society Symposium. Morrow, P., Black, B., Kobrinsky, M. J., Muthukumar, S., Nelson, D., Park, C.-H., and Webb, C. 2007. Design and fabrication of 3D microprocessors. In Proceedings of the Materials Research Society Symposium."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233573"},{"volume-title":"Proceedings of the Asia-South Pacific Design Automation Conference. 242--247","author":"Murali S.","key":"e_1_2_1_23_1","unstructured":"Murali , S. , Seiculescu , C. , Benini , L. , and Micheli , G. D . 2009. Synthesis of networks on chips for 3D systems on chips . In Proceedings of the Asia-South Pacific Design Automation Conference. 242--247 . Murali, S., Seiculescu, C., Benini, L., and Micheli, G. D. 2009. Synthesis of networks on chips for 3D systems on chips. In Proceedings of the Asia-South Pacific Design Automation Conference. 242--247."},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 1096--1101","author":"Ogras U. Y.","key":"e_1_2_1_24_1","unstructured":"Ogras , U. Y. and Marculescu , R . 2007. Analytical router modeling for networks-on-chip performance analysis . In Proceedings of the Design, Automation and Test in Europe. 1096--1101 . Ogras, U. Y. and Marculescu, R. 2007. Analytical router modeling for networks-on-chip performance analysis. In Proceedings of the Design, Automation and Test in Europe. 1096--1101."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1019151707785"},{"key":"e_1_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Pi\u00f3ro M. and Medhi D. 2004. Routing Flow and Capacity Design in Communication and Computer Networks. Morgan Kaufmann Publishers Inc. San Francisco CA. Pi\u00f3ro M. and Medhi D. 2004. Routing Flow and Capacity Design in Communication and Computer Networks . Morgan Kaufmann Publishers Inc. San Francisco CA.","DOI":"10.1016\/B978-012557189-0\/50011-1"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 9--14","author":"Seiculescu C.","key":"e_1_2_1_28_1","unstructured":"Seiculescu , C. , Murali , S. , Benini , L. , and Micheli , G. D . 2009. SunFloor 3D: A tool for networks on chip topology synthesis for 3D systems on chip . In Proceedings of the Design, Automation and Test in Europe. 9--14 . Seiculescu, C., Murali, S., Benini, L., and Micheli, G. D. 2009. SunFloor 3D: A tool for networks on chip topology synthesis for 3D systems on chip. In Proceedings of the Design, Automation and Test in Europe. 9--14."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 231--237","author":"Srinivasan K.","key":"e_1_2_1_29_1","unstructured":"Srinivasan , K. , Chatha , K. S. , and Konjevod , G . 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 231--237 . Srinivasan, K., Chatha, K. S., and Konjevod, G. 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 231--237."},{"volume-title":"Proceedings of the Annual IEEE\/ACM International Symposium on Microarchitecture. 294--305","author":"Wang H.","key":"e_1_2_1_30_1","unstructured":"Wang , H. , Zhu , X. , Peh , L.-S. , and Malik , S . 2002. Orion: A power-performance simulator for interconnection networks . In Proceedings of the Annual IEEE\/ACM International Symposium on Microarchitecture. 294--305 . Wang, H., Zhu, X., Peh, L.-S., and Malik, S. 2002. Orion: A power-performance simulator for interconnection networks. In Proceedings of the Annual IEEE\/ACM International Symposium on Microarchitecture. 294--305."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.810465"},{"volume-title":"Proceedings of the Asia-South Pacific Design Automation Conference. 277--282","author":"Yan S.","key":"e_1_2_1_32_1","unstructured":"Yan , S. and Lin , B . 2008a. Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees . In Proceedings of the Asia-South Pacific Design Automation Conference. 277--282 . Yan, S. and Lin, B. 2008a. Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees. In Proceedings of the Asia-South Pacific Design Automation Conference. 277--282."},{"volume-title":"Proceedings of the International Conference on Computer Design. 142--149","author":"Yan S.","key":"e_1_2_1_33_1","unstructured":"Yan , S. and Lin , B . 2008b. Design of application-specific 3D networks-on-chip architectures . In Proceedings of the International Conference on Computer Design. 142--149 . Yan, S. and Lin, B. 2008b. Design of application-specific 3D networks-on-chip architectures. In Proceedings of the International Conference on Computer Design. 142--149."},{"volume-title":"Proceedings of the Asia-South Pacific Design Automation Conference. 517--522","author":"Zhou P.","key":"e_1_2_1_34_1","unstructured":"Zhou , P. , Yuh , P.-H. , and Sapatnekar , S . 2010. Application-specific 3D network-on-chip design using simulated allocation . In Proceedings of the Asia-South Pacific Design Automation Conference. 517--522 . Zhou, P., Yuh, P.-H., and Sapatnekar, S. 2010. Application-specific 3D network-on-chip design using simulated allocation. In Proceedings of the Asia-South Pacific Design Automation Conference. 517--522."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2159542.2159544","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2159542.2159544","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:59:58Z","timestamp":1750244398000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2159542.2159544"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":34,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2012,4]]}},"alternative-id":["10.1145\/2159542.2159544"],"URL":"https:\/\/doi.org\/10.1145\/2159542.2159544","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2012,4]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-04-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}