{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:26:28Z","timestamp":1750307188153,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,3,25]],"date-time":"2012-03-25T00:00:00Z","timestamp":1332633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,3,25]]},"DOI":"10.1145\/2160916.2160952","type":"proceedings-article","created":{"date-parts":[[2012,3,27]],"date-time":"2012-03-27T15:17:28Z","timestamp":1332861448000},"page":"165-172","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Towards layout-friendly high-level synthesis"],"prefix":"10.1145","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA &amp; Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Liu","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guojie","family":"Luo","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raghu","family":"Prabhakar","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles, Los Angeles, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,25]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Altera Quartus II. Available: http:\/\/www.altera.com.  Altera Quartus II. Available: http:\/\/www.altera.com."},{"key":"e_1_3_2_1_2_1","unstructured":"Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 70731. Available: http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/.  Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 70731. Available: http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/."},{"key":"e_1_3_2_1_3_1","unstructured":"VPR and T-VPack 5.0.2. Available: http:\/\/www.eecg.toronto.edu\/vpr\/.  VPR and T-VPack 5.0.2. Available: http:\/\/www.eecg.toronto.edu\/vpr\/."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/553523"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/993483"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1015090.1015109"},{"key":"e_1_3_2_1_8_1","first-page":"690","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"Cheng C.-L. E.","year":"1994","unstructured":"C.-L. E. Cheng . Risa : accurate end efficient placement routability modeling . In Proc. Int. Conf. on Computer-Aided Design , pages 690 -- 695 , Nov. 1994 . C.-L. E. Cheng. Risa: accurate end efficient placement routability modeling. In Proc. Int. Conf. on Computer-Aided Design, pages 690--695, Nov. 1994."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920581"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283880"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825872"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233648"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687528"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228587"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1871230"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337769"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669124"},{"key":"e_1_3_2_1_20_1","first-page":"317","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"Fang Y.-M.","year":"1994","unstructured":"Y.-M. Fang and D. F. Wong . Simultaneous functional-unit binding and floorplanning . In Proc. Int. Conf. on Computer-Aided Design , pages 317 -- 321 , 1994 . Y.-M. Fang and D. F. Wong. Simultaneous functional-unit binding and floorplanning. In Proc. Int. Conf. on Computer-Aided Design, pages 317--321, 1994."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1007\/978-1-4020-8588-8_2","volume-title":"High-Level Synthesis: A Retrospective","author":"Gupta R.","year":"2008","unstructured":"R. Gupta and F. Brewer . High-Level Synthesis: A Retrospective , pages 13 -- 28 . Springer , 2008 . R. Gupta and F. Brewer. High-Level Synthesis: A Retrospective, pages 13--28. Springer, 2008."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123350"},{"key":"e_1_3_2_1_23_1","first-page":"435","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"Kim T.","year":"2007","unstructured":"T. Kim and X. Liu . Compatibility path based binding algorithm for interconnect reduction in high level synthesis . In Proc. Int. Conf. on Computer-Aided Design , pages 435 -- 441 , 2007 . T. Kim and X. Liu. Compatibility path based binding algorithm for interconnect reduction in high level synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 435--441, 2007."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811456"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/603095.603139"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884575"},{"key":"e_1_3_2_1_27_1","first-page":"578","volume-title":"Proc. European Conf. on Design Automation","author":"Liu S.","year":"1993","unstructured":"S. Liu , K.-R. Pan , M. Pedram , and A. Despain . Alleviating routing congestion by combining logic resynthesis and linear placement . In Proc. European Conf. on Design Automation , pages 578 -- 582 , Feb. 1993 . S. Liu, K.-R. Pan, M. Pedram, and A. Despain. Alleviating routing congestion by combining logic resynthesis and linear placement. In Proc. European Conf. on Design Automation, pages 578--582, Feb. 1993."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129917"},{"key":"e_1_3_2_1_29_1","first-page":"262","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"McFarland M. C.","year":"1987","unstructured":"M. C. McFarland . Reevaluating the design space for register transfer hardware synthesis . In Proc. Int. Conf. on Computer-Aided Design , pages 262 -- 265 , 1987 . M. C. McFarland. Reevaluating the design space for register transfer hardware synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 262--265, 1987."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/882452.874538"},{"key":"e_1_3_2_1_32_1","first-page":"536","volume-title":"Proc. Design Automation Conf.","author":"Pangre B. M.","year":"1988","unstructured":"B. M. Pangre . Splicer : a heuristic approach to connectivity binding . In Proc. Design Automation Conf. , pages 536 -- 541 , 1988 . B. M. Pangre. Splicer: a heuristic approach to connectivity binding. In Proc. Design Automation Conf., pages 536--541, 1988."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337749"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855969"},{"key":"e_1_3_2_1_35_1","volume-title":"Routing Congestion in VLSI Circuits: Estimation and Optimization","author":"Saxena P.","year":"2007","unstructured":"P. Saxena , R. S. Shelar , and S. S. Sapatnekar . Routing Congestion in VLSI Circuits: Estimation and Optimization . Springer , 2007 . P. Saxena, R. S. Shelar, and S. S. Sapatnekar. Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer, 2007."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781141"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289063"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1137\/1038003"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127748"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/268424.268425"}],"event":{"name":"ISPD'12: International Symposium on Physical Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Napa California USA","acronym":"ISPD'12"},"container-title":["Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2160916.2160952","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2160916.2160952","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:05:48Z","timestamp":1750241148000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2160916.2160952"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3,25]]},"references-count":40,"alternative-id":["10.1145\/2160916.2160952","10.1145\/2160916"],"URL":"https:\/\/doi.org\/10.1145\/2160916.2160952","relation":{},"subject":[],"published":{"date-parts":[[2012,3,25]]},"assertion":[{"value":"2012-03-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}