{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:30Z","timestamp":1763468070925,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Ingenio 2010 Consolider","award":["ESP00C-07-20811"],"award-info":[{"award-number":["ESP00C-07-20811"]}]},{"name":"Spanish government's research contracts","award":["TIN2008-005089"],"award-info":[{"award-number":["TIN2008-005089"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Comput. Syst."],"published-print":{"date-parts":[[2012,4]]},"abstract":"<jats:p>\n            Asymmetric multicore processors (AMPs) consist of cores with the same ISA (instruction-set architecture), but different microarchitectural features, speed, and power consumption. Because cores with more complex features and higher speed typically use more area and consume more energy relative to simpler and slower cores, we must use these cores for running applications that experience significant performance improvements from using those features. Having cores of different types in a single system allows optimizing the performance\/energy trade-off. To deliver this potential to unmodified applications, the OS scheduler must map threads to cores in consideration of the properties of both. Our work describes a\n            <jats:italic>Comprehensive<\/jats:italic>\n            scheduler for\n            <jats:italic>Asymmetric Multicore Processors<\/jats:italic>\n            (CAMP) that addresses shortcomings of previous asymmetry-aware schedulers. First, previous schedulers catered to only one kind of workload properties that are crucial for scheduling on AMPs; either\n            <jats:italic>efficiency<\/jats:italic>\n            or\n            <jats:italic>thread-level parallelism<\/jats:italic>\n            (TLP), but not both. CAMP overcomes this limitation showing how using both efficiency and TLP in synergy in a single scheduling algorithm can improve performance. Second, most existing schedulers relying on models for estimating how much faster a thread executes on a \u201cfast\u201d vs. \u201cslow\u201d core (i.e., the\n            <jats:italic>speedup factor<\/jats:italic>\n            ) were specifically designed for AMP systems where cores differ only in clock frequency. However, more realistic AMP systems include cores that differ more significantly in their features. To demonstrate the effectiveness of CAMP on more realistic scenarios, we augmented the CAMP scheduler with a model that predicts the speedup factor on a real AMP prototype that closely matches future asymmetric systems.\n          <\/jats:p>","DOI":"10.1145\/2166879.2166880","type":"journal-article","created":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T13:43:38Z","timestamp":1335879818000},"page":"1-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["Leveraging Core Specialization via OS Scheduling to Improve Performance on Asymmetric Multicore Systems"],"prefix":"10.1145","volume":"30","author":[{"given":"Juan Carlos","family":"Saez","sequence":"first","affiliation":[{"name":"Complutense University of Madrid"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandra","family":"Fedorova","sequence":"additional","affiliation":[{"name":"Simon Fraser University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Koufaty","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"Prieto","sequence":"additional","affiliation":[{"name":"Complutense University of Madrid"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.36"},{"key":"e_1_2_1_2_1","unstructured":"ARM. 2011. Big.LITTLE Processing with ARM CortexTM-A15 & Cortex-A7. White paper http:\/\/www.arm.com\/files\/downloads\/big_LITTLE_Final_Final.pdf. ARM . 2011. Big.LITTLE Processing with ARM CortexTM-A15 & Cortex-A7. White paper http:\/\/www.arm.com\/files\/downloads\/big_LITTLE_Final_Final.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070012"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1880018.1880019"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105745"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1026"},{"key":"e_1_2_1_8_1","unstructured":"Friedman J. H. 1999. Stochastic gradient boosting. www-stat.stanford.edu~jhf\/ftp\/stobst\/pdf. Friedman J. H. 1999. Stochastic gradient boosting. www-stat.stanford.edu~jhf\/ftp\/stobst\/pdf."},{"key":"e_1_2_1_9_1","unstructured":"Gillespie M. 2008. Preparing for the second stage of multi-core hardware: Asymmetric (heterogeneous) cores. Intel white paper. Gillespie M. 2008. Preparing for the second stage of multi-core hardware: Asymmetric (heterogeneous) cores. Intel white paper."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1656274.1656278"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755928"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956569"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006707"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362694"},{"volume-title":"Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA\u201910)","author":"Li T.","key":"e_1_2_1_16_1","unstructured":"Li , T. , Brett , P. , Knauerhase , R. , Koufaty , D. , Reddy , D. , and Hahn , S . 2010. Operating system support for overlapping-ISA heterogeneous multicore architectures . In Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA\u201910) . 1--12. Li, T., Brett, P., Knauerhase, R., Koufaty, D., Reddy, D., and Hahn, S. 2010. Operating system support for overlapping-ISA heterogeneous multicore architectures. In Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA\u201910). 1--12."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.47"},{"key":"e_1_2_1_18_1","unstructured":"Morad T. Weiser U. and Kolody A. 2004. ACCMP---Asymmetric cluster chip multi-processing. CCIT Tech. rep #448. Morad T. Weiser U. and Kolody A. 2004. ACCMP---Asymmetric cluster chip multi-processing. CCIT Tech. rep #448."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755929"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787281"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2010.08.020"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531793.1531804"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1353535.1346317"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1272996.1273004"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the International Workshop on OpenMP (IWOMP\u201905)","author":"van der Pas R.","year":"2005","unstructured":"van der Pas , R. 2005 . The OMPlab on Sun Systems . In Proceedings of the International Workshop on OpenMP (IWOMP\u201905) . van der Pas, R. 2005. The OMPlab on Sun Systems. In Proceedings of the International Workshop on OpenMP (IWOMP\u201905)."}],"container-title":["ACM Transactions on Computer Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2166879.2166880","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2166879.2166880","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:47Z","timestamp":1750240487000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2166879.2166880"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":26,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2012,4]]}},"alternative-id":["10.1145\/2166879.2166880"],"URL":"https:\/\/doi.org\/10.1145\/2166879.2166880","relation":{},"ISSN":["0734-2071","1557-7333"],"issn-type":[{"type":"print","value":"0734-2071"},{"type":"electronic","value":"1557-7333"}],"subject":[],"published":{"date-parts":[[2012,4]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-04-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}