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Therefore, current methodology involves designing compiler and architecture in isolation, leading to suboptimal performance of the final product.<\/jats:p>\n          <jats:p>\n            This article develops a novel approach to this\n            <jats:italic>codesign<\/jats:italic>\n            space problem. For our specific design space, we demonstrate that we can automatically predict the performance that an optimizing compiler would achieve without actually tuning it for any of the microarchitecture configurations considered. Once trained, a single run of the program compiled with the standard optimization setting is enough to make a prediction on the new microarchitecture with just a 3.2% error rate on average. This allows the designer to accurately choose an architectural configuration with knowledge of how an optimizing compiler will perform on it. We use this to find the best optimizing compiler\/architectural configuration in our codesign space and demonstrate that it achieves an average 19% performance improvement and energy savings of 16% compared to the baseline, nearly doubling the energy-efficiency measured as the energy-delay-squared product (EDD).\n          <\/jats:p>","DOI":"10.1145\/2180887.2180901","type":"journal-article","created":{"date-parts":[[2012,6,11]],"date-time":"2012-06-11T13:03:21Z","timestamp":1339419801000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy"],"prefix":"10.1145","volume":"11S","author":[{"given":"Christophe","family":"Dubach","sequence":"first","affiliation":[{"name":"University of Edinburgh"}]},{"given":"Timothy M.","family":"Jones","sequence":"additional","affiliation":[{"name":"University of Edinburgh"}]},{"given":"Michael F. P.","family":"O'Boyle","sequence":"additional","affiliation":[{"name":"University of Edinburgh"}]}],"member":"320","published-online":{"date-parts":[[2012,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354891"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2006.37"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/998300.997196"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176765"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.32"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/997163.997180"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1070891.1065921"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the INTERACT workshop at the International Symposium on High-Performance Computer Architecture.","author":"Desmet V.","unstructured":"Desmet , V. , Girbal , S. , and Temam , O . 2009. Archexplorer.org: Joint compiler\/hardware exploration for fair comparison of architectures . In Proceedings of the INTERACT workshop at the International Symposium on High-Performance Computer Architecture. Desmet, V., Girbal, S., and Temam, O. 2009. Archexplorer.org: Joint compiler\/hardware exploration for fair comparison of architectures. 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Intel XScale microarchitecture. http:\/\/www.intel.com\/design\/intelxscale\/. Intel Corporation . Intel XScale microarchitecture. http:\/\/www.intel.com\/design\/intelxscale\/."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/11549468_24"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture.","author":"Joseph P. J.","unstructured":"Joseph , P. J. , Vaswani , K. , and Thazhuthaveetil , M. J . 2006a. Construction and use of linear regression models for processor performance analysis . In Proceedings of the International Symposium on High-Performance Computer Architecture. Joseph, P. J., Vaswani, K., and Thazhuthaveetil, M. J. 2006a. Construction and use of linear regression models for processor performance analysis. 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