{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:55:33Z","timestamp":1750308933922,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,5,3]],"date-time":"2012-05-03T00:00:00Z","timestamp":1336003200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,5,3]]},"DOI":"10.1145\/2206781.2206785","type":"proceedings-article","created":{"date-parts":[[2012,5,7]],"date-time":"2012-05-07T18:47:53Z","timestamp":1336416473000},"page":"3-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Ambipolar double-gate FETs for the design of compact logic structures"],"prefix":"10.1145","author":[{"given":"Kotb","family":"Jabeur","sequence":"first","affiliation":[{"name":"Lyon Institute of Nanotechnology University of Lyon, Ecole Centrale de Lyon, F-69134 Ecully, France"}]},{"given":"Ian","family":"O'Connor","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology University of Lyon, Ecole Centrale de Lyon, F-69134 Ecully, France"}]},{"given":"Nataliya","family":"Yakymets","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology University of Lyon, Ecole Centrale de Lyon, F-69134 Ecully, France"}]},{"given":"S\u00e9bastien","family":"Le Beux","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology University of Lyon, Ecole Centrale de Lyon, F-69134 Ecully, France"}]}],"member":"320","published-online":{"date-parts":[[2012,5,3]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Emerging Research Devices","author":"International Technology TION","year":"2009","unstructured":"EDI TION International Technology Roadmap for Semiconductors : Emerging Research Devices , 2009 . EDITION International Technology Roadmap for Semiconductors: Emerging Research Devices, 2009."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077608"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.807446"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2004.1391610"},{"key":"e_1_3_2_1_5_1","volume-title":"IEDM Technical Digest, 555--558","author":"Appenzeller J.","year":"2006","unstructured":"J. Appenzeller \" Dual-gate nanowire transistors with nickel silicide contacts \", IEDM Technical Digest, 555--558 ( 2006 ). J. Appenzeller et al\"Dual-gate nanowire transistors with nickel silicide contacts\", IEDM Technical Digest, 555--558 (2006)."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941499"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Electronics Letters 2007 43 Double-Gate MOSFET based Reconfigurable Cells","DOI":"10.1049\/el:20072329"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.74"},{"volume-title":"IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10)","year":"2010","key":"e_1_3_2_1_9_1","unstructured":"Kotb. Jabeur et al, \"Reducing transistor count in clocked standard cells with ambipolar double-gate FETs \", IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10) , june 17-18 2010 , Anaheim, CA,USA. Kotb. Jabeur et al, \"Reducing transistor count in clocked standard cells with ambipolar double-gate FETs\", IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10), june 17-18 2010, Anaheim, CA,USA."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2082548"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1149\/1.3567706"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl803496s"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl049222b"},{"key":"e_1_3_2_1_14_1","volume-title":"Design, Automation and Test in Europe (DATE).","author":"Ben Jamaa M. H.","year":"2009","unstructured":"M. H. Ben Jamaa , \" Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis \", Design, Automation and Test in Europe (DATE). March 2009 . M. H. Ben Jamaa et al, \"Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis\", Design, Automation and Test in Europe (DATE). March 2009."},{"key":"e_1_3_2_1_15_1","first-page":"343","volume-title":"3rd IEEE-NANO","volume":"2","author":"Raychowdhury A.","year":"2003","unstructured":"A. Raychowdhury modeling of carbon nanotube FETs in the ballistic limit of performance\" in Proc . 3rd IEEE-NANO , 2003 , vol. 2 , pp. 343 -- 346 . A. Raychowdhury et al, \"Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance\" in Proc. 3rd IEEE-NANO, 2003, vol. 2, pp. 343--346."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1142\/S1793292008000952"},{"key":"e_1_3_2_1_17_1","first-page":"1","volume-title":"Int. Conf. DTISNanoscale Era","author":"Goguet J.","year":"2008","unstructured":"J. Goguet charge approach for a compact model of dual gate CNTFET\" in Proc . Int. Conf. DTISNanoscale Era , 2008 , pp. 1 -- 5 . J. Goguet et al, \"A charge approach for a compact model of dual gate CNTFET\" in Proc. Int. Conf. DTISNanoscale Era, 2008, pp. 1--5."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl035185x"},{"key":"e_1_3_2_1_20_1","unstructured":"http:\/\/ptm.asu.edu\/modelcard\/LP\/16nm_LP.pm  http:\/\/ptm.asu.edu\/modelcard\/LP\/16nm_LP.pm"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature01797"}],"event":{"name":"GLSVLSI '12: Great Lakes Symposium on VLSI 2012","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Salt Lake City Utah USA","acronym":"GLSVLSI '12"},"container-title":["Proceedings of the great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206785","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2206781.2206785","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:36:54Z","timestamp":1750282614000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206785"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5,3]]},"references-count":21,"alternative-id":["10.1145\/2206781.2206785","10.1145\/2206781"],"URL":"https:\/\/doi.org\/10.1145\/2206781.2206785","relation":{},"subject":[],"published":{"date-parts":[[2012,5,3]]},"assertion":[{"value":"2012-05-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}