{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,14]],"date-time":"2026-05-14T00:43:11Z","timestamp":1778719391842,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,5,3]],"date-time":"2012-05-03T00:00:00Z","timestamp":1336003200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,5,3]]},"DOI":"10.1145\/2206781.2206798","type":"proceedings-article","created":{"date-parts":[[2012,5,7]],"date-time":"2012-05-07T18:47:53Z","timestamp":1336416473000},"page":"63-66","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Parallel pipelined FFT architectures with reduced number of delays"],"prefix":"10.1145","author":[{"given":"Manohar","family":"Ayinala","sequence":"first","affiliation":[{"name":"University of Minnesota, Minneapolis, MN, USA"}]},{"given":"Keshab","family":"Parhi","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN, USA"}]}],"member":"320","published-online":{"date-parts":[[2012,5,3]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/35.722148"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2002.1012351"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1111\/j.1528-1167.2011.03138.x"},{"key":"e_1_3_2_1_4_1","first-page":"766","article-title":"A new approach to pipeline FFT processor","author":"He S.","year":"1996","unstructured":"S. He and M. Torkelson , \" A new approach to pipeline FFT processor ,\" Proc. of IPPS , 1996 , pp. 766 -- 770 . S. He and M. Torkelson, \"A new approach to pipeline FFT processor,\" Proc. of IPPS, 1996, pp. 766 -- 770.","journal-title":"Proc. of IPPS"},{"key":"e_1_3_2_1_5_1","first-page":"4719","volume-title":"Symp. on Circuits and Systems","author":"Lee J.","year":"2006","unstructured":"J. Lee , H. Lee , S. I. Cho and S. S. Choi , \" A High-Speed two parallel radix-24 FFT\/IFFT processor for MB-OFDM UWB systems,\" IEEE Inter . Symp. on Circuits and Systems , pp. 4719 -- 4722 , May 2006 . J. Lee, H. Lee, S. I. Cho and S. S. Choi, \"A High-Speed two parallel radix-24 FFT\/IFFT processor for MB-OFDM UWB systems,\" IEEE Inter. Symp. on Circuits and Systems, pp. 4719--4722, May 2006."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852007"},{"key":"e_1_3_2_1_7_1","first-page":"960","volume-title":"IEEE ISCAS 2008","author":"Shin M.","year":"2008","unstructured":"M. Shin and H. Lee , \" A high-speed four parallel radix-24 FFT\/IFFT processor for UWB applications \", IEEE ISCAS 2008 , pp. 960 -- 963 , May 2008 . M. Shin and H. Lee, \"A high-speed four parallel radix-24 FFT\/IFFT processor for UWB applications\", IEEE ISCAS 2008, pp. 960 -- 963, May 2008."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2147338"},{"key":"e_1_3_2_1_9_1","first-page":"374","volume-title":"Proc. IEEE APCCAS","author":"Wang Z.","year":"2006","unstructured":"Z. Wang A Novel FFT Processor for OFDM UWB Systems ,\" Proc. IEEE APCCAS , pp. 374 -- 377 , Dec. 2006 . Z. Wang et al., \"A Novel FFT Processor for OFDM UWB Systems,\" Proc. IEEE APCCAS, pp. 374--377, Dec. 2006."},{"key":"e_1_3_2_1_10_1","first-page":"582","volume-title":"Proc. IEEE WICOM","author":"Qiao S.","year":"2007","unstructured":"S. Qiao FFT Processor for UWB Systems ,\" Proc. IEEE WICOM , Sept. 2007 , pp. 582 -- 585 . S. Qiao et al., \"An Area and Power Efficient FFT Processor for UWB Systems,\" Proc. IEEE WICOM, Sept. 2007, pp. 582--585."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2048373"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.109555"},{"issue":"7","key":"e_1_3_2_1_13_1","first-page":"423","article-title":"Systematic synthesis of DSP data format converters using lifetime analysis and forward-backward register allocation","volume":"39","author":"Parhi K. K.","year":"1992","unstructured":"K. K. Parhi , \" Systematic synthesis of DSP data format converters using lifetime analysis and forward-backward register allocation ,\" IEEE TCAS - II , vol. 39 , no. 7 , pp. 423 -- 440 , July 1992 .. K. K. Parhi, \"Systematic synthesis of DSP data format converters using lifetime analysis and forward-backward register allocation,\" IEEE TCAS - II, vol. 39, no. 7, pp. 423--440, July 1992..","journal-title":"IEEE TCAS - II"}],"event":{"name":"GLSVLSI '12: Great Lakes Symposium on VLSI 2012","location":"Salt Lake City Utah USA","acronym":"GLSVLSI '12","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"]},"container-title":["Proceedings of the great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206798","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2206781.2206798","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:20:54Z","timestamp":1750238454000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206798"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5,3]]},"references-count":13,"alternative-id":["10.1145\/2206781.2206798","10.1145\/2206781"],"URL":"https:\/\/doi.org\/10.1145\/2206781.2206798","relation":{},"subject":[],"published":{"date-parts":[[2012,5,3]]},"assertion":[{"value":"2012-05-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}