{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:24:00Z","timestamp":1750307040697,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,5,3]],"date-time":"2012-05-03T00:00:00Z","timestamp":1336003200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,5,3]]},"DOI":"10.1145\/2206781.2206835","type":"proceedings-article","created":{"date-parts":[[2012,5,7]],"date-time":"2012-05-07T18:47:53Z","timestamp":1336416473000},"page":"221-226","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Modeling a single electron turnstile in HSPICE"],"prefix":"10.1145","author":[{"given":"Fabrizio","family":"Lombardi","sequence":"first","affiliation":[{"name":"Northeastern University, Boson, MA, USA"}]},{"given":"Wei","family":"Wei","sequence":"additional","affiliation":[{"name":"Northeastern University, Boston, MA, USA"}]},{"given":"Jie","family":"Han","sequence":"additional","affiliation":[{"name":"University of Alberta, Edmonton, AB, Canada"}]}],"member":"320","published-online":{"date-parts":[[2012,5,3]]},"reference":[{"volume-title":"Int. Electron. Devices Meet. 251--254","author":"Yu B.","key":"e_1_3_2_1_1_1","unstructured":"Yu , B. , Chang , L. , Ahmed , S. et al. 2002. FinFET scaling to 10 nm gate length . Int. Electron. Devices Meet. 251--254 . Yu, B., Chang, L., Ahmed, S. et al. 2002. FinFET scaling to 10 nm gate length. Int. Electron. Devices Meet. 251--254."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513944"},{"volume-title":"NSF Nanoscale Science and Engineering Grantees Conference.","author":"Redwing J.","key":"e_1_3_2_1_3_1","unstructured":"Redwing , J. , Mayer , T. , Mohney , S. et al. 2002. Semiconductor nanowires: building blocks for nanoscale electronics . NSF Nanoscale Science and Engineering Grantees Conference. Redwing, J., Mayer, T., Mohney, S. et al. 2002. Semiconductor nanowires: building blocks for nanoscale electronics. NSF Nanoscale Science and Engineering Grantees Conference."},{"key":"e_1_3_2_1_4_1","volume-title":"et al","author":"Peatman W.C.B.","year":"1994","unstructured":"Peatman , W.C.B. , Brown , E.R. , Rooks , M.J. et al . 1994 . Novel resonant tunneling transistor with high transconductance at room temperature. IEEE Electron. Device Lett . 15 (7). Peatman, W.C.B., Brown, E.R., Rooks, M.J. et al. 1994. Novel resonant tunneling transistor with high transconductance at room temperature. IEEE Electron. Device Lett. 15 (7)."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.55277"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.284.5412.289"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/14\/4\/311"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1116\/1.1491551"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1038\/39535"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1070\/PU1998v041n02ABEH000364"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.658562"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.1004237"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.777155"},{"volume-title":"Solitons Fractals.","author":"Oya T.","key":"e_1_3_2_1_14_1","unstructured":"Oya , T. , Asai , T. and Amemiya , Y . Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks. Chaos , Solitons Fractals. Vol. 32 , 855--861. Oya, T., Asai, T. and Amemiya, Y. Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks. Chaos, Solitons Fractals. Vol. 32, 855--861."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675860"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.808421"},{"volume-title":"Nanoelectronic Circuit Architectures Based on Single-Electron Turntiles. 2nd IEEE International Nanoelectronics Conference. 978-1-4244-1573-1.","author":"Zhang W. C.","key":"e_1_3_2_1_17_1","unstructured":"Zhang , W. C. and Wu , N. J . 2008 . Nanoelectronic Circuit Architectures Based on Single-Electron Turntiles. 2nd IEEE International Nanoelectronics Conference. 978-1-4244-1573-1. Zhang, W. C. and Wu, N. J. 2008. Nanoelectronic Circuit Architectures Based on Single-Electron Turntiles. 2nd IEEE International Nanoelectronics Conference. 978-1-4244-1573-1."},{"volume-title":"Error mechanisms and rates in tunable-barrier single-electron turnstiles and charge-coupled devices. J. Appl. Phys","author":"Zimmermana N. M.","key":"e_1_3_2_1_18_1","unstructured":"Zimmermana , N. M. , Hourdakis , E. , Ono , Y. , Fujiwara , A. and Takahashi , Y . Error mechanisms and rates in tunable-barrier single-electron turnstiles and charge-coupled devices. J. Appl. Phys . Vol. 96 , 5254--5266. Zimmermana, N. M., Hourdakis, E., Ono, Y., Fujiwara, A. and Takahashi, Y. Error mechanisms and rates in tunable-barrier single-electron turnstiles and charge-coupled devices. J. Appl. Phys. Vol. 96, 5254--5266."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20040195"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Nara Y. 2009. Scaling challenges of MOSFET for 32 nm node and beyond. VLSI Technology System and Application. 72--73. Nara Y. 2009. Scaling challenges of MOSFET for 32 nm node and beyond. VLSI Technology System and Application. 72--73.","DOI":"10.1109\/VTSA.2009.5159296"}],"event":{"name":"GLSVLSI '12: Great Lakes Symposium on VLSI 2012","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Salt Lake City Utah USA","acronym":"GLSVLSI '12"},"container-title":["Proceedings of the great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206835","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2206781.2206835","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:20:54Z","timestamp":1750238454000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2206781.2206835"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5,3]]},"references-count":20,"alternative-id":["10.1145\/2206781.2206835","10.1145\/2206781"],"URL":"https:\/\/doi.org\/10.1145\/2206781.2206835","relation":{},"subject":[],"published":{"date-parts":[[2012,5,3]]},"assertion":[{"value":"2012-05-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}