{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:24:16Z","timestamp":1750307056019,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2012,6]]},"abstract":"<jats:p>Multicore Systems-on-Chip (MCSoC) are comprised of a rich set of processor cores, specialized hardware accelerators, and I\/O interfaces. Functional verification of these complex designs is a critical and demanding task, however, focusing only on functional verification is very risky because the motivation for building such systems in the first place is to achieve high levels of system throughput. Therefore a functionally correct MCSoC that does not exhibit sufficient performance will fail in the market. In addition, limiting performance verification efforts to analyzing individual system components in isolation is insufficient due to: (1) the degree of system-level resource contention that an application domain imposes on the MCSoC, and (2) the degree of configuration flexibility that is typically afforded by an MCSoC. These factors motivate system-level performance verification of MCSoC. This article presents an important industrial case study of MCSoC performance verification involving both pre- and postsilicon analysis, highlighting the methodology used, the lessons learned, and recommendations for improvement.<\/jats:p>","DOI":"10.1145\/2209291.2209294","type":"journal-article","created":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T17:35:16Z","timestamp":1343842516000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["A full lifecycle performance verification methodology for multicore systems-on-chip"],"prefix":"10.1145","volume":"17","author":[{"given":"Jim","family":"Holt","sequence":"first","affiliation":[{"name":"Freescale Semiconductor, Inc. &amp; Massachusetts Institute of Technology"}]},{"given":"Jaideep","family":"Dastidar","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor, Inc., Austin, Texas"}]},{"given":"David","family":"Lindberg","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor, Inc., Austin, Texas"}]},{"given":"John","family":"Pape","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor, Inc., Austin, Texas"}]},{"given":"Peng","family":"Yang","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor, Inc., Austin, Texas"}]}],"member":"320","published-online":{"date-parts":[[2012,7,5]]},"reference":[{"volume-title":"Proceedings of the International Solid State Circuits Conference.","author":"Bell S.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278499"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.675637"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2006.26"},{"volume-title":"Proceedings of the 2nd Workshop on Architecture Research Using FPGA Platforms.","author":"Chiou D.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","unstructured":"Freescale Semiconductor. 2008. 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