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Syst."],"published-print":{"date-parts":[[2012,7]]},"abstract":"<jats:p>\n            An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC\u2019s .18\n            <jats:italic>um<\/jats:italic>\n            CMOS technology for the binary field size of 163 is also presented.\n          <\/jats:p>","DOI":"10.1145\/2220336.2220343","type":"journal-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T13:42:45Z","timestamp":1343742165000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["An Efficient Finite Field Multiplier Using Redundant Representation"],"prefix":"10.1145","volume":"11","author":[{"given":"Ashkan Hosseinzadeh","family":"Namin","sequence":"first","affiliation":[{"name":"University of Windsor"}]},{"given":"Huapeng","family":"Wu","sequence":"additional","affiliation":[{"name":"University of Windsor"}]},{"given":"Majid","family":"Ahmadi","sequence":"additional","affiliation":[{"name":"University of Windsor"}]}],"member":"320","published-online":{"date-parts":[[2012,7]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"0\n   .18&mu;m TSMC CMOS Technology 1999. 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