{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:27Z","timestamp":1750307007355,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,3]],"date-time":"2012-06-03T00:00:00Z","timestamp":1338681600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,3]]},"DOI":"10.1145\/2228360.2228543","type":"proceedings-article","created":{"date-parts":[[2012,5,31]],"date-time":"2012-05-31T12:10:51Z","timestamp":1338466251000},"page":"1012-1017","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Alternate hammering test for application-specific DRAMs and an industrial case study"],"prefix":"10.1145","author":[{"given":"Rei-Fu","family":"Huang","sequence":"first","affiliation":[{"name":"MediaTek Inc., Hsinchu, Taiwan"}]},{"given":"Hao-Yu","family":"Yang","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Mango C.-T.","family":"Chao","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Shih-Chin","family":"Lin","sequence":"additional","affiliation":[{"name":"United Microelectronics Corp., Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2012,6,3]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE International Electron Devices Meeting","author":"Tran T.","year":"2006","unstructured":"T. Tran , A 58nm Trench DRAM Technology ,\" IEEE International Electron Devices Meeting , 2006 . T. Tran, et al., \"A 58nm Trench DRAM Technology,\" IEEE International Electron Devices Meeting, 2006."},{"key":"e_1_3_2_1_2_1","volume-title":"A 64 Mbit DRAM trench capacitor cell with field-plate isolation,\" International Symposium on VLSI Technology, Systems, and Applications","author":"Teng C. W.","year":"1991","unstructured":"C. W. Teng , Y. Okumoto , J. Liu , Ih-Chin Chen , K. Yuhara , and Y. Yoneoka , \" A 64 Mbit DRAM trench capacitor cell with field-plate isolation,\" International Symposium on VLSI Technology, Systems, and Applications , 1991 . C. W. Teng, Y. Okumoto, J. Liu, Ih-Chin Chen, K. Yuhara, and Y. Yoneoka, \"A 64 Mbit DRAM trench capacitor cell with field-plate isolation,\" International Symposium on VLSI Technology, Systems, and Applications, 1991."},{"key":"e_1_3_2_1_3_1","volume-title":"Integration of capacitor for sub-100-nm DRAM trench technology,\" Symposium on VLSI Technology","author":"Lutzen J.","year":"2002","unstructured":"J. Lutzen , , \" Integration of capacitor for sub-100-nm DRAM trench technology,\" Symposium on VLSI Technology , 2002 . J. Lutzen, et al., \"Integration of capacitor for sub-100-nm DRAM trench technology,\" Symposium on VLSI Technology, 2002."},{"key":"e_1_3_2_1_4_1","volume-title":"Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering,\" IEEE International Electron Devices Meeting","author":"Pawlak M. A.","year":"2010","unstructured":"M. A. Pawlak , , \" Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering,\" IEEE International Electron Devices Meeting , 2010 . M. A. Pawlak, et al., \"Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering,\" IEEE International Electron Devices Meeting, 2010."},{"key":"e_1_3_2_1_5_1","volume-title":"Scalability of TiN\/HfAlO\/TiN MIM DRAM capacitor to 0.7-nm-EOT and beyond,\" IEEE International Electron Devices Meeting","author":"Mise N.","year":"2009","unstructured":"N. Mise , , \" Scalability of TiN\/HfAlO\/TiN MIM DRAM capacitor to 0.7-nm-EOT and beyond,\" IEEE International Electron Devices Meeting , 2009 . N. Mise, et al., \"Scalability of TiN\/HfAlO\/TiN MIM DRAM capacitor to 0.7-nm-EOT and beyond,\" IEEE International Electron Devices Meeting, 2009."},{"key":"e_1_3_2_1_6_1","volume-title":"0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications,\" IEEE International Electron Devices Meeting","author":"Menou N.","year":"2008","unstructured":"N. Menou , , \" 0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications,\" IEEE International Electron Devices Meeting , 2008 . N. Menou, et al., \"0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications,\" IEEE International Electron Devices Meeting, 2008."},{"key":"e_1_3_2_1_7_1","volume-title":"A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications,\" International Electron Devices Meeting","author":"Wang G.","year":"2006","unstructured":"G. Wang , , \" A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications,\" International Electron Devices Meeting , 2006 . G. Wang, et al., \"A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications,\" International Electron Devices Meeting, 2006."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2084470"},{"key":"e_1_3_2_1_9_1","volume-title":"Solid-State Device Research Conference","author":"Berthelot A.","year":"2006","unstructured":"A. Berthelot , Highly Reliable TiN\/ZrO2\/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies ,\" Solid-State Device Research Conference , 2006 . A. Berthelot, et al., \"Highly Reliable TiN\/ZrO2\/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies,\" Solid-State Device Research Conference, 2006."},{"key":"e_1_3_2_1_10_1","first-page":"59","volume-title":"Design and Testing","author":"Vollrath J.","year":"2000","unstructured":"J. Vollrath , \"Tutorial : Synchronous Dynamic Memory Test Construction - A Field Approach,\" IEEE International Workshop on Memory Technology , Design and Testing , pp. 59 -- 64 , 2000 . J. Vollrath, \"Tutorial: Synchronous Dynamic Memory Test Construction - A Field Approach,\" IEEE International Workshop on Memory Technology, Design and Testing, pp. 59--64, 2000."},{"key":"e_1_3_2_1_11_1","first-page":"1120","volume-title":"IEEE International Test Conference","author":"McConnell R.","year":"1998","unstructured":"R. McConnell , U. Moller , D. Richter , \" How we test Siemens Embedded DRAM Cores ,\" IEEE International Test Conference , pp. 1120 -- 1125 , 1998 . R. McConnell, U. Moller, D. Richter, \"How we test Siemens Embedded DRAM Cores,\" IEEE International Test Conference, pp. 1120--1125, 1998."},{"key":"e_1_3_2_1_12_1","first-page":"426","volume-title":"IEEE International Test Conference","author":"van de Goor A. J.","year":"2000","unstructured":"A. J. van de Goor , A. Paalvast , \" Industrial Evaluation of DRAM SIMM Tests ,\" IEEE International Test Conference , pp. 426 -- 435 , 2000 . A. J. van de Goor, A. Paalvast, \"Industrial Evaluation of DRAM SIMM Tests,\" IEEE International Test Conference, pp. 426--435, 2000."},{"key":"e_1_3_2_1_13_1","first-page":"1","article-title":"DRAM-Specific Space of Memory Tests","author":"Al-Ars Z.","year":"2006","unstructured":"Z. Al-Ars , S. Hamdioui , A. J. van de Goor , G. Gaydadjiev , J. Vollrath , \" DRAM-Specific Space of Memory Tests ,\" IEEE International Test Conference , pp. 1 -- 10 , 2006 . Z. Al-Ars, S. Hamdioui, A. J. van de Goor, G. Gaydadjiev, J. Vollrath, \"DRAM-Specific Space of Memory Tests,\" IEEE International Test Conference, pp. 1--10, 2006.","journal-title":"IEEE International Test Conference"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630097"},{"key":"e_1_3_2_1_15_1","first-page":"1","article-title":"Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs","author":"Al-Ars Z.","year":"2008","unstructured":"Z. Al-Ars , S. Hamdioui , A. J. van de Goor , G. Mueller , \" Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs ,\" IEEE International Test Conference , pp. 1 -- 10 , 2008 . Z. Al-Ars, S. Hamdioui, A. J. van de Goor, G. Mueller, \"Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs,\" IEEE International Test Conference, pp. 1--10, 2008.","journal-title":"IEEE International Test Conference"}],"event":{"name":"DAC '12: The 49th Annual Design Automation Conference 2012","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '12"},"container-title":["Proceedings of the 49th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2228360.2228543","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2228360.2228543","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:58Z","timestamp":1750236538000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2228360.2228543"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6,3]]},"references-count":15,"alternative-id":["10.1145\/2228360.2228543","10.1145\/2228360"],"URL":"https:\/\/doi.org\/10.1145\/2228360.2228543","relation":{},"subject":[],"published":{"date-parts":[[2012,6,3]]},"assertion":[{"value":"2012-06-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}