{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:28Z","timestamp":1750307008206,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,3]],"date-time":"2012-06-03T00:00:00Z","timestamp":1338681600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2009-TJ-1879"],"award-info":[{"award-number":["2009-TJ-1879"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,3]]},"DOI":"10.1145\/2228360.2228587","type":"proceedings-article","created":{"date-parts":[[2012,5,31]],"date-time":"2012-05-31T12:10:51Z","timestamp":1338466251000},"page":"1239-1244","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A metric for layout-friendly microarchitecture optimization in high-level synthesis"],"prefix":"10.1145","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[{"name":"University of California, Los Angeles"}]},{"given":"Bin","family":"Liu","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}]}],"member":"320","published-online":{"date-parts":[[2012,6,3]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Handel-C Language Reference Manual","author":"Agility Design Solutions Inc.","year":"2007","unstructured":"Agility Design Solutions Inc. Handel-C Language Reference Manual , 2007 . Agility Design Solutions Inc. Handel-C Language Reference Manual, 2007."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1080\/10556789908805765"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/993483"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1015090.1015109"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283880"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825872"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233648"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160952"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337769"},{"key":"e_1_3_2_1_10_1","first-page":"317","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"Fang Y.-M.","year":"1994","unstructured":"Y.-M. Fang and D. F. Wong . Simultaneous functional-unit binding and floorplanning . In Proc. Int. Conf. on Computer-Aided Design , pages 317 -- 321 , 1994 . Y.-M. Fang and D. F. Wong. Simultaneous functional-unit binding and floorplanning. In Proc. Int. Conf. on Computer-Aided Design, pages 317--321, 1994."},{"key":"e_1_3_2_1_11_1","first-page":"57","article-title":"Laplacian of graphs and algebraic connectivity","volume":"25","author":"Fiedler M.","year":"1989","unstructured":"M. Fiedler . Laplacian of graphs and algebraic connectivity . Combinatorics and Graph Theory , 25 : 57 -- 70 , 1989 . M. Fiedler. Laplacian of graphs and algebraic connectivity. Combinatorics and Graph Theory, 25:57--70, 1989.","journal-title":"Combinatorics and Graph Theory"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1002\/jgt.20502"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895780"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123350"},{"key":"e_1_3_2_1_15_1","first-page":"435","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"Kim T.","year":"2007","unstructured":"T. Kim and X. Liu . Compatibility path based binding algorithm for interconnect reduction in high level synthesis . In Proc. Int. Conf. on Computer-Aided Design , pages 435 -- 441 , 2007 . T. Kim and X. Liu. Compatibility path based binding algorithm for interconnect reduction in high level synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 435--441, 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.49"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811456"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/110316.149327"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"e_1_3_2_1_20_1","first-page":"262","volume-title":"Proc. Int. Conf. on Computer-Aided Design","author":"McFarland M. C.","year":"1987","unstructured":"M. C. McFarland . Reevaluating the design space for register transfer hardware synthesis . In Proc. Int. Conf. on Computer-Aided Design , pages 262 -- 265 , 1987 . M. C. McFarland. Reevaluating the design space for register transfer hardware synthesis. In Proc. Int. Conf. on Computer-Aided Design, pages 262--265, 1987."},{"key":"e_1_3_2_1_21_1","first-page":"536","volume-title":"Proc. Design Automation Conf.","author":"Pangre B. M.","year":"1988","unstructured":"B. M. Pangre . Splicer : a heuristic approach to connectivity binding . In Proc. Design Automation Conf. , pages 536 -- 541 , 1988 . B. M. Pangre. Splicer: a heuristic approach to connectivity binding. In Proc. Design Automation Conf., pages 536--541, 1988."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/0196-6774(86)90023-4"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1137\/1038003"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127748"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1111\/0081-1750.00098"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842820"}],"event":{"name":"DAC '12: The 49th Annual Design Automation Conference 2012","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '12"},"container-title":["Proceedings of the 49th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2228360.2228587","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2228360.2228587","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:59Z","timestamp":1750236539000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2228360.2228587"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6,3]]},"references-count":27,"alternative-id":["10.1145\/2228360.2228587","10.1145\/2228360"],"URL":"https:\/\/doi.org\/10.1145\/2228360.2228587","relation":{},"subject":[],"published":{"date-parts":[[2012,6,3]]},"assertion":[{"value":"2012-06-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}