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News"],"published-print":{"date-parts":[[2012,5,31]]},"abstract":"<jats:p>Execution of arithmetic operations at a very high speed in real time is the major concern in compute intensive digital signal processing (DSP) algorithms Residue Number Systems are being considered as alternative to binary number system because of their capabilities of performing \"carry free\" arithmetic operations. However, RNS systems have so far been used to handle integer numbers only. Floating Point RNS arithmetic units have obvious advantages over fixed point multiply &amp; accumulate (MAC) units which are the key units in Digital Signal Processors. Keeping this in view, in this paper, the architecture of a floating point MAC unit is presented.<\/jats:p>","DOI":"10.1145\/2234336.2234343","type":"journal-article","created":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T15:51:28Z","timestamp":1338565888000},"page":"39-43","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["\"Floating point RNS\""],"prefix":"10.1145","volume":"40","author":[{"given":"Aniruddha","family":"Ghosh","sequence":"first","affiliation":[{"name":"West Bengal University of Technology, Salt Lake, Kolkata, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satrughna","family":"Singha","sequence":"additional","affiliation":[{"name":"JIS College of Engineering, Kalyani, Nadia, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amitabha","family":"Sinha","sequence":"additional","affiliation":[{"name":"West Bengal University of Technology, Salt Lake, Kolkata, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,5,31]]},"reference":[{"volume-title":"Briggs","author":"Kai Hwang (Purdue University","key":"e_1_2_1_1_1"},{"volume-title":"A Wiley-Inter science Publication","year":"1999","author":"Mitra Sanjit K.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","volume-title":"McGraw-Hill","author":"Hayes J.P","year":"1998","edition":"3"},{"key":"e_1_2_1_4_1","first-page":"044705","volume-title":"TATA McGRAW-HILL EDITION","author":"Sanjit K.","year":"2001"},{"key":"e_1_2_1_5_1","unstructured":"www.ieee.org (Institute of Electrical and Electronics Engineers Inc.).  www.ieee.org (Institute of Electrical and Electronics Engineers Inc.)."},{"volume-title":"Virtex Platform FPGA","year":"2004","author":"Introduction","key":"e_1_2_1_6_1"},{"volume-title":"1983 IEEE Internal Conference on Computer Design: VLSI in Computers (ICCCD'83)","year":"1983","author":"Chiang Chao-Lin","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1984.1659138"},{"volume-title":"NAFIPS 2005 - 2005 Annual Meeting of the North American Fuzzy Information Processing Society, IEEE Press","year":"2005","author":"Setiaarif Eep","key":"e_1_2_1_9_1"},{"volume-title":"Modulii Selection in RNS for Efficient VLSI Implementation","year":"2003","author":"Wang Wei","key":"e_1_2_1_10_1"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112613"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1998.678160"},{"key":"e_1_2_1_13_1","unstructured":"J. Ramirez A. Garcia L. Parrilla P.G. Fernandez A. Lloris \"A Novel RNS-Based SIMD RISC Processor For Digital Signal Processing\" IEEE Press.  J. Ramirez A. Garcia L. Parrilla P.G. Fernandez A. Lloris \"A Novel RNS-Based SIMD RISC Processor For Digital Signal Processing\" IEEE Press."},{"volume-title":"Principles,Architectures and VLSI Design,\" Integrated System Laboratory","year":"1999","author":"Computer Arithmetic Reto Zimmermann","key":"e_1_2_1_14_1"},{"volume-title":"International Journal of Computer Science and Communication, Volume-1, Number-2","year":"2010","author":"Ghosh A.","key":"e_1_2_1_15_1"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2234336.2234343","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2234336.2234343","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:00:43Z","timestamp":1750276843000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2234336.2234343"}},"subtitle":["a new concept for designing the MAC unit of digital signal processor"],"short-title":[],"issued":{"date-parts":[[2012,5,31]]},"references-count":15,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2012,5,31]]}},"alternative-id":["10.1145\/2234336.2234343"],"URL":"https:\/\/doi.org\/10.1145\/2234336.2234343","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2012,5,31]]},"assertion":[{"value":"2012-05-31","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}