{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:50:36Z","timestamp":1750308636378,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,5,15]],"date-time":"2012-05-15T00:00:00Z","timestamp":1337040000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,5,15]]},"DOI":"10.1145\/2236576.2236579","type":"proceedings-article","created":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T15:51:57Z","timestamp":1338565917000},"page":"22-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Exploration of heuristic scheduling algorithms for 3D multicore processors"],"prefix":"10.1145","author":[{"given":"Thomas Canhao","family":"Xu","sequence":"first","affiliation":[{"name":"University of Turku, Turku, Finland"}]},{"given":"Pasi","family":"Liljeberg","sequence":"additional","affiliation":[{"name":"University of Turku, Turku, Finland"}]},{"given":"Juha","family":"Plosila","sequence":"additional","affiliation":[{"name":"University of Turku, Turku, Finland"}]},{"given":"Hannu","family":"Tenhunen","sequence":"additional","affiliation":[{"name":"University of Turku, Turku, Finland"}]}],"member":"320","published-online":{"date-parts":[[2012,5,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_2_1","unstructured":"Intel: Intel research areas on microarchitecture (January 2012) http:\/\/techresearch.intel.com\/projecthome.aspx?ResearchAreaId=11.  Intel: Intel research areas on microarchitecture (January 2012) http:\/\/techresearch.intel.com\/projecthome.aspx?ResearchAreaId=11."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.288614"},{"key":"e_1_3_2_1_4_1","unstructured":"AMD\n  : The amd opteron 6000 series platform (January 2012) http:\/\/www.amd.com\/us\/products\/server\/processors\/6000-series-platform\/pages\/6000-series-platform.aspx.  AMD: The amd opteron 6000 series platform (January 2012) http:\/\/www.amd.com\/us\/products\/server\/processors\/6000-series-platform\/pages\/6000-series-platform.aspx."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.18"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.13"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.108"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.65"},{"key":"e_1_3_2_1_9_1","volume-title":"Beyne","author":"Velenis D.","year":"2009","unstructured":"Velenis , D. , Stucchi , M. , Marinissen , E. , Swinnen , B. , Beyne , E. : Impact of 3d design choices on manufacturing cost. In : IEEE 3DIC 2009 . (Sept. 2009) 1--5 Velenis, D., Stucchi, M., Marinissen, E., Swinnen, B., Beyne, E.: Impact of 3d design choices on manufacturing cost. In: IEEE 3DIC 2009. (Sept. 2009) 1--5"},{"volume-title":"Design and Diagnostics of Electronic Circuits Systems (DDECS), 2011 IEEE 14th International Symposium on. (april 2011)","author":"Xu T.","key":"e_1_3_2_1_10_1","unstructured":"Xu , T. , Liljeberg , P. , Tenhunen , H. : Optimal number and placement of through silicon vias in 3d network-on-chip . In: Design and Diagnostics of Electronic Circuits Systems (DDECS), 2011 IEEE 14th International Symposium on. (april 2011) 105--110 Xu, T., Liljeberg, P., Tenhunen, H.: Optimal number and placement of through silicon vias in 3d network-on-chip. In: Design and Diagnostics of Electronic Circuits Systems (DDECS), 2011 IEEE 14th International Symposium on. (april 2011) 105--110"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/98457.98761"},{"issue":"5","key":"e_1_3_2_1_12_1","first-page":"729","article-title":"Efficient scheduling algorithms for robot inverse dynamics computation on a multiprocessor system. Systems, Man and Cybernetics","volume":"18","author":"Chen C.","year":"1988","unstructured":"Chen , C. , Lee , C. , Hou , E. : Efficient scheduling algorithms for robot inverse dynamics computation on a multiprocessor system. Systems, Man and Cybernetics , IEEE Transactions on 18 ( 5 ) ( 1988 ) 729 -- 743 Chen, C., Lee, C., Hou, E.: Efficient scheduling algorithms for robot inverse dynamics computation on a multiprocessor system. Systems, Man and Cybernetics, IEEE Transactions on 18(5) (1988) 729--743","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.175"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.473519"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264206"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2009.02.002"},{"key":"e_1_3_2_1_17_1","volume-title":"DATE '04","author":"Hu J.","year":"2004","unstructured":"Hu , J. , Marculescu , R. : Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints . In: DATE '04 , Washington, DC, USA, IEEE Computer Society ( 2004 ) 10234 Hu, J., Marculescu, R.: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: DATE '04, Washington, DC, USA, IEEE Computer Society (2004) 10234"},{"key":"e_1_3_2_1_18_1","volume-title":"Hot chips","author":"IBM","year":"2009","unstructured":"IBM : Ibm power 7 processor . In: Hot chips 2009 . (August 2009) IBM: Ibm power 7 processor. In: Hot chips 2009. (August 2009)"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523067"},{"volume-title":"Proceedings of the 27th Norchip Conference. (November 2009)","author":"Xu T. C.","key":"e_1_3_2_1_20_1","unstructured":"Xu , T. C. , Yin , A. W. , Liljeberg , P. , Tenhunen , H. : A study of 3d network-on-chip design for data parallel h.264 coding . In: Proceedings of the 27th Norchip Conference. (November 2009) Xu, T. C., Yin, A. W., Liljeberg, P., Tenhunen, H.: A study of 3d network-on-chip design for data parallel h.264 coding. In: Proceedings of the 27th Norchip Conference. (November 2009)"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147160"},{"key":"e_1_3_2_1_23_1","unstructured":"Ltd. S. E. C.: Samsung develops 30nm-class 32gb green ddr3 for next-generation servers using tsv package technology (January 2012) http:\/\/www.samsung.com\/global\/business\/semiconductor\/newsView.do?news_id=1253.  Ltd. S. E. C.: Samsung develops 30nm-class 32gb green ddr3 for next-generation servers using tsv package technology (January 2012) http:\/\/www.samsung.com\/global\/business\/semiconductor\/newsView.do?news_id=1253."},{"volume-title":"Advanced Packaging Materials (APM), 2011 International Symposium on. (oct. 2011)","author":"Lau J. H.","key":"e_1_3_2_1_24_1","unstructured":"Lau , J. H. : Evolution, challenge, and outlook of tsv, 3d ic integration and 3d silicon integration . In: Advanced Packaging Materials (APM), 2011 International Symposium on. (oct. 2011) 462 --488 Lau, J. H.: Evolution, challenge, and outlook of tsv, 3d ic integration and 3d silicon integration. In: Advanced Packaging Materials (APM), 2011 International Symposium on. (oct. 2011) 462 --488"},{"key":"e_1_3_2_1_25_1","unstructured":"Association S. I.: The international technology roadmap for semiconductors (itrs) (2007) http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.htm.  Association S. I.: The international technology roadmap for semiconductors (itrs) (2007) http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.htm."},{"volume-title":"Proc. of the 60th ECTC. (2010)","author":"Lau J. H.","key":"e_1_3_2_1_26_1","unstructured":"Lau , J. H. : Tsv manufacturing yield and hidden costs for 3d ic integration . In: Proc. of the 60th ECTC. (2010) 1031 --1042 Lau, J. H.: Tsv manufacturing yield and hidden costs for 3d ic integration. In: Proc. of the 60th ECTC. (2010) 1031 --1042"},{"key":"e_1_3_2_1_27_1","volume-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual","author":"Corporation","year":"2011","unstructured":"Corporation , I. : Intel 64 and IA-32 Architectures Optimization Reference Manual . Intel Corporation ( 2011 ) Corporation, I.: Intel 64 and IA-32 Architectures Optimization Reference Manual. Intel Corporation (2011)"},{"key":"e_1_3_2_1_28_1","volume-title":"Wilcox","author":"Fischer T.","year":"2011","unstructured":"Fischer , T. , Arekapudi , S. , Busta , E. , Dietz , C. , Golden , M. , Hilker , S. , Horiuchi , A. , Hurd , K. , Johnson , D. , McIntyre , H. , Naffziger , S. , Vinh , J. , White , J. , Wilcox , K. : Design solutions for the bulldozer 32nm soi 2-core processor module in an 8-core cpu. In: 2011 IEEE ISSCC. ( feb. 2011) 78 --80 Fischer, T., Arekapudi, S., Busta, E., Dietz, C., Golden, M., Hilker, S., Horiuchi, A., Hurd, K., Johnson, D., McIntyre, H., Naffziger, S., Vinh, J., White, J., Wilcox, K.: Design solutions for the bulldozer 32nm soi 2-core processor module in an 8-core cpu. In: 2011 IEEE ISSCC. (feb. 2011) 78 --80"},{"key":"e_1_3_2_1_29_1","unstructured":"Wasson S.: A quick look at bulldozer thread scheduling (January 2012) http:\/\/techreport.com\/articles.x\/21865.  Wasson S.: A quick look at bulldozer thread scheduling (January 2012) http:\/\/techreport.com\/articles.x\/21865."},{"key":"e_1_3_2_1_30_1","first-page":"180","volume-title":"DSD","author":"Lei T.","year":"2003","unstructured":"Lei , T. , Kumar , S. : A two-step genetic algorithm for mapping task graphs to a network on chip architecture . In: DSD , 2003 . (sep. 2003) 180 -- 187 Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: DSD, 2003. (sep. 2003) 180--187"},{"volume-title":"Proceedings of the 16th International Parallel and Distributed Processing Symposium. (April 2002)","author":"Gaeke B. R.","key":"e_1_3_2_1_31_1","unstructured":"Gaeke , B. R. , Husbands , P. , Li , X. S. , Oliker , L. , Yelick , K. A. , Biswas , R. : Memory-intensive benchmarks: Iram vs. cache-based machines . In: Proceedings of the 16th International Parallel and Distributed Processing Symposium. (April 2002) 203 Gaeke, B. R., Husbands, P., Li, X. S., Oliker, L., Yelick, K. A., Biswas, R.: Memory-intensive benchmarks: Iram vs. cache-based machines. In: Proceedings of the 16th International Parallel and Distributed Processing Symposium. (April 2002) 203"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039405"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393988"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00162341"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/113379.113380"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_38_1","volume-title":": Resource Management in the Solaris 9 Operating Environment. Sun Microsystems","author":"Lawson S. J.","year":"2002","unstructured":"Lawson , S. J. : Resource Management in the Solaris 9 Operating Environment. Sun Microsystems , Inc . ( 2002 ) Lawson, S. J.: Resource Management in the Solaris 9 Operating Environment. Sun Microsystems, Inc. (2002)"},{"key":"e_1_3_2_1_39_1","volume-title":"Gagne","author":"Silberschatz A.","year":"2008","unstructured":"Silberschatz , A. , Galvin , P. B. , Gagne , G. : Operating System Concepts. Wiley ( 2008 ) Silberschatz, A., Galvin, P. B., Gagne, G.: Operating System Concepts. Wiley (2008)"}],"event":{"name":"Map2MPSoC\/SCOPES'12: Workshop on Software and Compilers for Embedded Systems","sponsor":["EDAA European Design Automation Association","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Sankt Goar Germany","acronym":"Map2MPSoC\/SCOPES'12"},"container-title":["Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2236576.2236579","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2236576.2236579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:08:06Z","timestamp":1750273686000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2236576.2236579"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5,15]]},"references-count":38,"alternative-id":["10.1145\/2236576.2236579","10.1145\/2236576"],"URL":"https:\/\/doi.org\/10.1145\/2236576.2236579","relation":{},"subject":[],"published":{"date-parts":[[2012,5,15]]},"assertion":[{"value":"2012-05-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}