{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T14:39:30Z","timestamp":1769956770322,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,16]],"date-time":"2012-06-16T00:00:00Z","timestamp":1339804800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,16]]},"DOI":"10.1145\/2247684.2247690","type":"proceedings-article","created":{"date-parts":[[2012,6,11]],"date-time":"2012-06-11T13:03:31Z","timestamp":1339419811000},"page":"21-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Rank idle time prediction driven last-level cache writeback"],"prefix":"10.1145","author":[{"given":"Zhe","family":"Wang","sequence":"first","affiliation":[{"name":"The University of Texas at San Antonio"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samira M.","family":"Khan","sequence":"additional","affiliation":[{"name":"The University of Texas at San Antonio"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel A.","family":"Jim\u00e9nez","sequence":"additional","affiliation":[{"name":"The University of Texas at San Antonio"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,6,16]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"DDR3 SDRAM standard JEDEC JESD79-3. http:\/\/www.jedec.org.  DDR3 SDRAM standard JEDEC JESD79-3. http:\/\/www.jedec.org."},{"key":"e_1_3_2_1_2_1","volume-title":"Disk. Elseiver","author":"Jacob S. B.","year":"2008","unstructured":"S. B. Jacob and D. T. Wang . The Memory Systems - Cache, Dram , Disk. Elseiver , 2008 . S. B. Jacob and D. T. Wang. The Memory Systems - Cache, Dram, Disk. Elseiver, 2008."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966491"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.4"},{"key":"e_1_3_2_1_6_1","volume-title":"Intel 875P chipset datasheet: Intel 82875P memory controller hub (MCH)","author":"Intel Corporation","year":"2004","unstructured":"Intel Corporation . Intel 875P chipset datasheet: Intel 82875P memory controller hub (MCH) . 2004 . Intel Corporation. Intel 875P chipset datasheet: Intel 82875P memory controller hub (MCH). 2004."},{"key":"e_1_3_2_1_7_1","volume-title":"Intel 82945G\/82945GZ\/82945GC graphics and memory controller hub (GMCH) and Intel 82945P\/82945PL memory controller hub (MCH)","author":"Intel Corporation","year":"2008","unstructured":"Intel Corporation . Intel 945G\/945GZ\/945GC\/945P\/945PL express chipset family datasheet : Intel 82945G\/82945GZ\/82945GC graphics and memory controller hub (GMCH) and Intel 82945P\/82945PL memory controller hub (MCH) . 2008 . Intel Corporation. Intel 945G\/945GZ\/945GC\/945P\/945PL express chipset family datasheet: Intel 82945G\/82945GZ\/82945GC graphics and memory controller hub (GMCH) and Intel 82945P\/82945PL memory controller hub (MCH). 2008."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360132"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966495"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054954"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346206"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815972"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736045"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03138-0_14"}],"event":{"name":"PLDI '12: ACM SIGPLAN Conference on Programming Language Design and Implementation","location":"Beijing China","acronym":"PLDI '12","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2247684.2247690","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2247684.2247690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:50Z","timestamp":1750273670000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2247684.2247690"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6,16]]},"references-count":21,"alternative-id":["10.1145\/2247684.2247690","10.1145\/2247684"],"URL":"https:\/\/doi.org\/10.1145\/2247684.2247690","relation":{},"subject":[],"published":{"date-parts":[[2012,6,16]]},"assertion":[{"value":"2012-06-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}