{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,17]],"date-time":"2025-12-17T17:54:33Z","timestamp":1765994073916,"version":"3.41.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T00:00:00Z","timestamp":1343779200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["702628","856039"],"award-info":[{"award-number":["702628","856039"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2012,8]]},"abstract":"<jats:p>A fast method to identify the given Boolean function as a threshold function with weight assignment is introduced. It characterizes the function based on the parameters that have been defined in the literature. The proposed method is capable to quickly characterize all functions that have less than eight inputs and has been shown to operate fast for functions with as many as forty inputs. Furthermore, comparisons with other existing heuristic methods show huge increase in the number of threshold functions identified, and drastic reduction in time and complexity.<\/jats:p>","DOI":"10.1145\/2287696.2287702","type":"journal-article","created":{"date-parts":[[2012,8,21]],"date-time":"2012-08-21T13:06:30Z","timestamp":1345554390000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["An efficient heuristic to identify threshold logic functions"],"prefix":"10.1145","volume":"8","author":[{"given":"Ashok Kumar","family":"Palaniswamy","sequence":"first","affiliation":[{"name":"Southern Illinois University Carbondale, Carbondale, IL"}]},{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[{"name":"Southern Illinois University Carbondale, Carbondale, IL"}]}],"member":"320","published-online":{"date-parts":[[2012,8,15]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1018419.1019651"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1009665432594"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.816365"},{"volume-title":"Proceedings of the IEEE International Symposium on Micro NanoMechatronics and Human Science 2. 930--935","author":"Beiu V.","key":"e_1_2_1_4_1","unstructured":"Beiu , V. , Quintana , J. M. , Avedillo , M. J. , and Sulieman , M . 2003b. Threshold logic: from vacuum tubes to nanoelectronics . In Proceedings of the IEEE International Symposium on Micro NanoMechatronics and Human Science 2. 930--935 . Beiu, V., Quintana, J. M., Avedillo, M. J., and Sulieman, M. 2003b. Threshold logic: from vacuum tubes to nanoelectronics. In Proceedings of the IEEE International Symposium on Micro NanoMechatronics and Human Science 2. 930--935."},{"key":"e_1_2_1_5_1","first-page":"489","article-title":"Differential implementations of threshold logic gates","volume":"2","author":"Beiu V.","year":"2003","unstructured":"Beiu , V. , Quintana , J. M. , Avedilo , M. J. , and Andonie , R. 2003 c. Differential implementations of threshold logic gates . In Proceedings of the International Symposium on Signals, Circuits and Systems 2. 489 -- 492 . Beiu, V., Quintana, J. M., Avedilo, M. J., and Andonie, R. 2003c. Differential implementations of threshold logic gates. In Proceedings of the International Symposium on Signals, Circuits and Systems 2. 489--492.","journal-title":"Proceedings of the International Symposium on Signals, Circuits and Systems"},{"volume-title":"Proceedings of the International Conference on Computer Design. 235--240","author":"Bobba S.","key":"e_1_2_1_6_1","unstructured":"Bobba , S. and Hajj , I. N . 2000. Current mode threshold logic gates . In Proceedings of the International Conference on Computer Design. 235--240 . Bobba, S. and Hajj, I. N. 2000. Current mode threshold logic gates. In Proceedings of the International Conference on Computer Design. 235--240."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123222"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"volume-title":"Proceedings of the 7th IEEE International Conference on Electronics, Circuits and Systems. 932--935","author":"Celinski P.","key":"e_1_2_1_9_1","unstructured":"Celinski , P. , AlSarawi , S. , and Abbott , D . 2000. Delay analysis of neuron mos and capacitive threshold logic . In Proceedings of the 7th IEEE International Conference on Electronics, Circuits and Systems. 932--935 . Celinski, P., AlSarawi, S., and Abbott, D. 2000. Delay analysis of neuron mos and capacitive threshold logic. In Proceedings of the 7th IEEE International Conference on Electronics, Circuits and Systems. 932--935."},{"key":"e_1_2_1_10_1","volume-title":"Threshold Logic: A Synthesis Approach","author":"Dertouzos M. L.","year":"1965","unstructured":"Dertouzos , M. L. 1965 . Threshold Logic: A Synthesis Approach . MIT Press , Cambridge, MA . Dertouzos, M. L. 1965. Threshold Logic: A Synthesis Approach. MIT Press, Cambridge, MA."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1260725"},{"volume-title":"Proceedings of the International Joint Conference on Neural Networks. 4791--4796","author":"Franco L.","key":"e_1_2_1_12_1","unstructured":"Franco , L. , Subirats , J. L. , Anthony , M. , and Jerez , J. M . 2006. A new constructive approach for creating all linearly separable (threshold) functions . In Proceedings of the International Joint Conference on Neural Networks. 4791--4796 . Franco, L., Subirats, J. L., Anthony, M., and Jerez, J. M. 2006. A new constructive approach for creating all linearly separable (threshold) functions. In Proceedings of the International Joint Conference on Neural Networks. 4791--4796."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.44"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. 125--130","author":"Gowda T.","key":"e_1_2_1_14_1","unstructured":"Gowda , T. and Vrudhula , S . 2008. Decomposition based approach for synthesis of multi-level threshold logic circuits . In Proceedings of the Asia and South Pacific Design Automation Conference. 125--130 . Gowda, T. and Vrudhula, S. 2008. Decomposition based approach for synthesis of multi-level threshold logic circuits. In Proceedings of the Asia and South Pacific Design Automation Conference. 125--130."},{"key":"e_1_2_1_15_1","unstructured":"Hachtel G. D. and Somenzi F. 2006. Logic Synthesis and Verification Algorithms. Springer.   Hachtel G. D. and Somenzi F. 2006. Logic Synthesis and Verification Algorithms. Springer."},{"volume-title":"Switching and Finite Automata Theory","author":"Kohavi Z.","key":"e_1_2_1_16_1","unstructured":"Kohavi , Z. 1990. Switching and Finite Automata Theory . McGraw-Hill Higher Education . Kohavi, Z. 1990. Switching and Finite Automata Theory. McGraw-Hill Higher Education."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2007.18"},{"volume-title":"Threshold Logic and Its Applications","author":"Muroga S.","key":"e_1_2_1_18_1","unstructured":"Muroga , S. 1971. Threshold Logic and Its Applications . John Wiley and Sons , New York . Muroga, S. 1971. Threshold Logic and Its Applications. John Wiley and Sons, New York."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-62-99195-0"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.223046"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1374376.1374450"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1981.12139"},{"volume-title":"Proceedings of the 13th WSEAS International Conference on Circuits. 162--167","author":"Palaniswamy A. K.","key":"e_1_2_1_23_1","unstructured":"Palaniswamy , A. K. , Goparaju , M. K. , and Tragoudas , S . 2009. A fault tolerant threshold logic gate design . In Proceedings of the 13th WSEAS International Conference on Circuits. 162--167 . Palaniswamy, A. K., Goparaju, M. K., and Tragoudas, S. 2009. A fault tolerant threshold logic gate design. In Proceedings of the 13th WSEAS International Conference on Circuits. 162--167."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785545"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.42"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925943"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674745"},{"volume-title":"Proceedings of the 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era.","author":"Shinogi T.","key":"e_1_2_1_28_1","unstructured":"Shinogi , T. , Arakawa , K. , and Hayashi , T . 2009. Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing . In Proceedings of the 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era. Shinogi, T., Arakawa, K., and Hayashi, T. 2009. Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing. In Proceedings of the 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era."},{"key":"e_1_2_1_29_1","volume-title":"Cudd: Cu decision diagram package release 2.3.1","author":"Somenzi F.","year":"2001","unstructured":"Somenzi , F. 2001 . Cudd: Cu decision diagram package release 2.3.1 . University of Colorado at Boulder. Somenzi, F. 2001. Cudd: Cu decision diagram package release 2.3.1. University of Colorado at Boulder."},{"key":"e_1_2_1_30_1","first-page":"3188","article-title":"A new decomposition algorithm for threshold synthesis and generalization of boolean functions","volume":"55","author":"Subirats J. L.","year":"2008","unstructured":"Subirats , J. L. , Jerez , J. M. , and Franco , L. 2008 . A new decomposition algorithm for threshold synthesis and generalization of boolean functions . IEEE Trans. Circ. Syst. 55 , 10, 3188 -- 3196 . Subirats, J. L., Jerez, J. M., and Franco, L. 2008. A new decomposition algorithm for threshold synthesis and generalization of boolean functions. IEEE Trans. Circ. Syst. 55, 10, 3188--3196.","journal-title":"IEEE Trans. Circ. Syst."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222665"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/321637.321647"},{"volume-title":"Proceedings of the16th Annual Workshop on Circuits, Systems and Signal Processing. 578--583","author":"Zhang L.","key":"e_1_2_1_33_1","unstructured":"Zhang , L. and Cotofana , S . 2005. An input weights aware synthesis tool for threshold logic networks . In Proceedings of the16th Annual Workshop on Circuits, Systems and Signal Processing. 578--583 . Zhang, L. and Cotofana, S. 2005. An input weights aware synthesis tool for threshold logic networks. In Proceedings of the16th Annual Workshop on Circuits, Systems and Signal Processing. 578--583."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839468(410) 24"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2287696.2287702","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2287696.2287702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:49:04Z","timestamp":1750236544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2287696.2287702"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":34,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2012,8]]}},"alternative-id":["10.1145\/2287696.2287702"],"URL":"https:\/\/doi.org\/10.1145\/2287696.2287702","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2012,8]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-08-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}