{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:18Z","timestamp":1750306998903,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":50,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,25]],"date-time":"2012-06-25T00:00:00Z","timestamp":1340582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,25]]},"DOI":"10.1145\/2304576.2304587","type":"proceedings-article","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:31:21Z","timestamp":1340803881000},"page":"59-68","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["UniFI"],"prefix":"10.1145","author":[{"given":"Somayeh","family":"Sardashti","sequence":"first","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI, USA"}]},{"given":"David A.","family":"Wood","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI, USA"}]}],"member":"320","published-online":{"date-parts":[[2012,6,25]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Proc. of the 31st Annual Intnl. Symp. on Computer Architecture (June","author":"Alameldeen A.","year":"2004","unstructured":"Alameldeen , A. , and Wood , D . 2004. Adaptive Cache Compression for High-Performance Processors . In Proc. of the 31st Annual Intnl. Symp. on Computer Architecture (June 2004 ). Alameldeen, A., and Wood, D. 2004. Adaptive Cache Compression for High-Performance Processors. In Proc. of the 31st Annual Intnl. Symp. on Computer Architecture (June 2004)."},{"key":"e_1_3_2_1_2_1","volume-title":"Proc. of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads (Feb.","author":"Alameldeen A.","year":"2002","unstructured":"Alameldeen , A. , Mauer , C. , Xu , M. , Harper , P. , Martin , M. , Sorin , D. , Hill , M. , and Wood , D . 2002. Evaluating Non-deterministic Multi-threaded Commercial Workloads . In Proc. of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads (Feb. 2002 ). Alameldeen, A., Mauer, C., Xu, M., Harper, P., Martin, M., Sorin, D., Hill, M., and Wood, D. 2002. Evaluating Non-deterministic Multi-threaded Commercial Workloads. In Proc. of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads (Feb. 2002)."},{"key":"e_1_3_2_1_3_1","volume-title":"SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools (July","author":"Aslot V.","year":"2001","unstructured":"Aslot , V. , Domeika , M. , Eigenmann , R. , Gaertner , G. , Jones , W. , and Parady , B . 2001 . SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools (July 2001 ). Aslot, V., Domeika, M., Eigenmann, R., Gaertner, G., Jones, W., and Parady, B. 2001. SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools (July 2001)."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"volume-title":"Proc. of the conference on Design, automation and test in Europe.","author":"Borkar S.","key":"e_1_3_2_1_5_1","unstructured":"Borkar , S. , Jouppi , N. , and Stenstrom , P . 2007. Microprocessors in the era of terascale integration . In Proc. of the conference on Design, automation and test in Europe. Borkar, S., Jouppi, N., and Stenstrom, P. 2007. Microprocessors in the era of terascale integration. In Proc. of the conference on Design, automation and test in Europe."},{"volume-title":"Proc. of the 14th IEEE Symp. on High-Performance Computer Architectur.","author":"Das R.","key":"e_1_3_2_1_6_1","unstructured":"Das , R. , Mishra , A. , Nicopoulos , C. , Park , D. , Narayanan , V. , Iyer , R. , Yousif , M. , and Das , C . 2008. Performance and power optimization through data compression in Network-on-Chip architectures . In Proc. of the 14th IEEE Symp. on High-Performance Computer Architectur. Das, R., Mishra, A., Nicopoulos, C., Park, D., Narayanan, V., Iyer, R., Yousif, M., and Das, C. 2008. Performance and power optimization through data compression in Network-on-Chip architectures. In Proc. of the 14th IEEE Symp. on High-Performance Computer Architectur."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654117"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346194"},{"key":"e_1_3_2_1_9_1","volume-title":"Proc. of the 5th IEEE Symp. on High-Performance Computer Architecture (January","author":"Hagersten E.","year":"1999","unstructured":"Hagersten , E. , and Koster , M . 1999. WildFire: A Scalable Path for SMPs . In Proc. of the 5th IEEE Symp. on High-Performance Computer Architecture (January 1999 ). Hagersten, E., and Koster, M. 1999. WildFire: A Scalable Path for SMPs. In Proc. of the 5th IEEE Symp. on High-Performance Computer Architecture (January 1999)."},{"key":"e_1_3_2_1_10_1","volume-title":"Process integration, devices, and structures","author":"International","year":"2009","unstructured":"International technology roadmap for semiconductors. Process integration, devices, and structures , 2009 . International technology roadmap for semiconductors. Process integration, devices, and structures, 2009."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669116"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816012"},{"key":"e_1_3_2_1_22_1","volume-title":"Proc. of the IEEE.","author":"Zhu J.","year":"2008","unstructured":"Zhu , J. 2008 . Magnetoresistive Random AccessMemory: The Path to Competitiveness and Scalability . In Proc. of the IEEE. Zhu, J. 2008. Magnetoresistive Random AccessMemory: The Path to Competitiveness and Scalability. In Proc. of the IEEE."},{"volume-title":"Implications of Storage Class Memories (SCM) on Software Architectures. In HPCA 2010 Workshop on the use of Emerging Storage and memory Technologies (WEST).","author":"Mohan C.","key":"e_1_3_2_1_23_1","unstructured":"Mohan , C. , and Bhattacharya , S . 2010 . Implications of Storage Class Memories (SCM) on Software Architectures. In HPCA 2010 Workshop on the use of Emerging Storage and memory Technologies (WEST). Mohan, C., and Bhattacharya, S. 2010. Implications of Storage Class Memories (SCM) on Software Architectures. In HPCA 2010 Workshop on the use of Emerging Storage and memory Technologies (WEST)."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545228"},{"key":"e_1_3_2_1_25_1","volume-title":"Proc. of the 29th Annual Intnl. Symp. on Computer Architecture (May","author":"Sorin D.","year":"2002","unstructured":"Sorin , D. , Martin , M. , Hill , M. , and Wood , D . 2002. SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint\/Recovery . In Proc. of the 29th Annual Intnl. Symp. on Computer Architecture (May 2002 ). Sorin, D., Martin, M., Hill, M., and Wood, D. 2002. SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint\/Recovery. In Proc. of the 29th Annual Intnl. Symp. on Computer Architecture (May 2002)."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.100"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2009.341"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_30_1","volume-title":"Technical Report HPL-2008--20, Hewlett Packard Labs.","author":"Shyamkumar T.","year":"2008","unstructured":"Shyamkumar , T. , Muralimanohar , N. , Ahn , J. , and Jouppi , N . 2008 . CACTI 5.1. Technical Report HPL-2008--20, Hewlett Packard Labs. Shyamkumar, T., Muralimanohar, N., Ahn, J., and Jouppi, N. 2008. CACTI 5.1. Technical Report HPL-2008--20, Hewlett Packard Labs."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.75069"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.8"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508269"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.443"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_1_37_1","unstructured":"Alameldeenand A. Wood D. 2003. Variability in architectural simulations of multi-threaded workloads. In HPCA.   Alameldeenand A. Wood D. 2003. Variability in architectural simulations of multi-threaded workloads. In HPCA."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859474"},{"key":"e_1_3_2_1_39_1","volume-title":"T., Flautner, K.","author":"Das S.","year":"2004","unstructured":"Das , S. , Pant , S. , Rao , R. , Pham , T. , Ziesler , C. , Blaauw , D. , Austin , T., Flautner, K. , and Mudge, T. 2004 . Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation, IEEE MICRO (Dec . 2004). Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., and Mudge, T. 2004. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, IEEE MICRO (Dec. 2004)."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859631"},{"key":"e_1_3_2_1_41_1","volume-title":"Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA (June","author":"Miller T.","year":"2009","unstructured":"Miller , T. , Surapaneni , N. , Teodorescu , R. , and Degroat , J . 2009. Flexible Redundancy in Robust Processor Architecture , Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA (June 2009 ). Miller, T., Surapaneni, N., Teodorescu, R., and Degroat, J. 2009. Flexible Redundancy in Robust Processor Architecture, Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA (June 2009)."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.54"},{"volume-title":"Architecture Design for Soft Errors","author":"Mukherjee S.","key":"e_1_3_2_1_43_1","unstructured":"Mukherjee , S. 2008. Architecture Design for Soft Errors . Elsevier Inc . Mukherjee, S. 2008. Architecture Design for Soft Errors. Elsevier Inc."},{"volume-title":"Intl. Symp. on High-Perf. Com, Arch.","author":"Nakano J.","key":"e_1_3_2_1_44_1","unstructured":"Nakano , J. , Montesinos , P. , Gharachorloo , K. , and Torrellas , J . 2006. ReViveI\/O: Efficient handling of I\/O in highly-available rollback-recovery servers . Intl. Symp. on High-Perf. Com, Arch. Nakano, J., Montesinos, P., Gharachorloo, K., and Torrellas, J. 2006. ReViveI\/O: Efficient handling of I\/O in highly-available rollback-recovery servers. Intl. Symp. on High-Perf. Com, Arch."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000083"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"Ghasemi H. Draper S. and Kim N. 2011. Low-Voltage On-Chip Cache Architecture using Heterogeneous Cell Sizes for Multi-Core Processors. In HPCA.   Ghasemi H. Draper S. and Kim N. 2011. Low-Voltage On-Chip Cache Architecture using Heterogeneous Cell Sizes for Multi-Core Processors. In HPCA.","DOI":"10.1109\/HPCA.2011.5749715"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545232"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"}],"event":{"name":"ICS'12: International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"San Servolo Island, Venice Italy","acronym":"ICS'12"},"container-title":["Proceedings of the 26th ACM international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304587","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2304576.2304587","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:47Z","timestamp":1750236527000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304587"}},"subtitle":["leveraging non-volatile memories for a unified fault tolerance and idle power management technique"],"short-title":[],"issued":{"date-parts":[[2012,6,25]]},"references-count":50,"alternative-id":["10.1145\/2304576.2304587","10.1145\/2304576"],"URL":"https:\/\/doi.org\/10.1145\/2304576.2304587","relation":{},"subject":[],"published":{"date-parts":[[2012,6,25]]},"assertion":[{"value":"2012-06-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}