{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:18Z","timestamp":1750306998294,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,25]],"date-time":"2012-06-25T00:00:00Z","timestamp":1340582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,25]]},"DOI":"10.1145\/2304576.2304598","type":"proceedings-article","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:31:21Z","timestamp":1340803881000},"page":"153-162","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Enhancing the performance of assisted execution runtime systems through hardware\/software techniques"],"prefix":"10.1145","author":[{"given":"Gokcen","family":"Kestor","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"given":"Roberto","family":"Gioiosa","sequence":"additional","affiliation":[{"name":"Pacific Northwest National Laboratory, Richland, WA, USA"}]},{"given":"Osman Sabri","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"IIIA - CSIC - Spanish National Research Council, Barcelona, Spain"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"Universitat Politecnica de Catalunya, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2012,6,25]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Performance guide for HPC applications on IBM power 755 system","author":"Abeles J.","year":"2010","unstructured":"J. Abeles , L. Brochard , L. Capps , D. DeSota , J. Edwards , B. Elkin , J. Lewars , E. Michel , R. Panda , R. Ravindran , J. Robichaux , S. Kandadai , and S. Vemuganti . Performance guide for HPC applications on IBM power 755 system , 2010 . J. Abeles, L. Brochard, L. Capps, D. DeSota, J. Edwards, B. Elkin, J. Lewars, E. Michel, R. Panda, R. Ravindran, J. Robichaux, S. Kandadai, and S. Vemuganti. Performance guide for HPC applications on IBM power 755 system, 2010."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.8"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536293"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1413370.1413412"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.446.0885"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.37"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950373"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693464"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168900"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/11864219_14"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.516.0639"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477488"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2010.5648812"},{"key":"e_1_3_2_1_16_1","volume-title":"Intel AtomTM processor n450, d410 and d510 for embedded applications","author":"Intel Corporation","year":"2010","unstructured":"Intel Corporation . Intel AtomTM processor n450, d410 and d510 for embedded applications , 2010 . Document Number: 323439-001 EN , revision 1.0. Intel Corporation. Intel AtomTM processor n450, d410 and d510 for embedded applications, 2010. Document Number: 323439-001 EN, revision 1.0."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.54"},{"key":"e_1_3_2_1_19_1","first-page":"2","volume-title":"Proc. of the 15th IEEE Int. Parallel & Distributed Processing Symposium","author":"Luo K.","unstructured":"K. Luo , M. Franklin , S. S. Mukherjee , and A. Seznec . Boosting SMT performance by speculation control . In Proc. of the 15th IEEE Int. Parallel & Distributed Processing Symposium , pages 2 --, 2001. K. Luo, M. Franklin, S. S. Mukherjee, and A. Seznec. Boosting SMT performance by speculation control. In Proc. of the 15th IEEE Int. Parallel & Distributed Processing Symposium, pages 2--, 2001."},{"key":"e_1_3_2_1_20_1","volume-title":"MLP-Aware Dynamic Cache Partitioning. Int. Conference on High Performance Embedded Architectures and Compilers","author":"Moreto M.","year":"2008","unstructured":"M. Moreto , F. J. Cazorla , A. Ramirez , and M. Valero . MLP-Aware Dynamic Cache Partitioning. Int. Conference on High Performance Embedded Architectures and Compilers , 2008 . M. Moreto, F. J. Cazorla, A. Ramirez, and M. Valero. MLP-Aware Dynamic Cache Partitioning. Int. Conference on High Performance Embedded Architectures and Compilers, 2008."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161046"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2190025.2190055"},{"key":"e_1_3_2_1_23_1","volume-title":"Workshop on Operating System Interference in High Performance Applications","author":"Meswani M. R.","year":"2006","unstructured":"M. R. Meswani and P. J. Teller . Evaluating the performance impact of hardware thread priorities in simultaneous multithreaded processors using SPEC CPU2000 . In Workshop on Operating System Interference in High Performance Applications , 2006 . M. R. Meswani and P. J. Teller. Evaluating the performance impact of hardware thread priorities in simultaneous multithreaded processors using SPEC CPU2000. In Workshop on Operating System Interference in High Performance Applications, 2006."},{"key":"e_1_3_2_1_24_1","volume-title":"Proc. of the IEEE Intl. Symp. on Workload Characterization","author":"Minh C. C.","year":"2008","unstructured":"C. C. Minh , J. Chung , C. Kozyrakis , and K. Olukotun . STAMP: Stanford transactional applications for multi-processing . In Proc. of the IEEE Intl. Symp. on Workload Characterization , 2008 . C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proc. of the IEEE Intl. Symp. on Workload Characterization, 2008."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342006064503"},{"key":"e_1_3_2_1_26_1","volume-title":"WoTUG-18","author":"Pillet V.","year":"1995","unstructured":"V. Pillet , J. Labarta , T. Cortes , and S. Girona . PARAVER: A tool to visualize and analyze parallel code. Technical report , In WoTUG-18 , 1995 . V. Pillet, J. Labarta, T. Cortes, and S. Girona. PARAVER: A tool to visualize and analyze parallel code. Technical report, In WoTUG-18, 1995."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248415"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2127330"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/1148882.1148884"},{"key":"e_1_3_2_1_30_1","volume-title":"Proc. of the 4th ACM SIGPLAN Workshop on Transactional Computing","author":"Spear M. F.","year":"2009","unstructured":"M. F. Spear , A. Shriraman , L. Dalessandro , and M. L. Scott . Transactional mutex locks . In Proc. of the 4th ACM SIGPLAN Workshop on Transactional Computing , Raleigh, NC, USA , Feb. 2009 . M. F. Spear, A. Shriraman, L. Dalessandro, and M. L. Scott. Transactional mutex locks. In Proc. of the 4th ACM SIGPLAN Workshop on Transactional Computing, Raleigh, NC, USA, Feb. 2009."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320114"}],"event":{"name":"ICS'12: International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"San Servolo Island, Venice Italy","acronym":"ICS'12"},"container-title":["Proceedings of the 26th ACM international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304598","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2304576.2304598","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:47Z","timestamp":1750236527000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304598"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6,25]]},"references-count":29,"alternative-id":["10.1145\/2304576.2304598","10.1145\/2304576"],"URL":"https:\/\/doi.org\/10.1145\/2304576.2304598","relation":{},"subject":[],"published":{"date-parts":[[2012,6,25]]},"assertion":[{"value":"2012-06-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}