{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T06:27:07Z","timestamp":1776925627607,"version":"3.51.2"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,6,25]],"date-time":"2012-06-25T00:00:00Z","timestamp":1340582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,6,25]]},"DOI":"10.1145\/2304576.2304613","type":"proceedings-article","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:31:21Z","timestamp":1340803881000},"page":"257-266","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Multiple sub-row buffers in DRAM"],"prefix":"10.1145","author":[{"given":"Nagendra Dwarakanath","family":"Gulur","sequence":"first","affiliation":[{"name":"Texas Instruments (India) Pvt Ltd, Bangalore, India"}]},{"given":"R.","family":"Manikantan","sequence":"additional","affiliation":[{"name":"Indian Institute of Science, Bangalore, India"}]},{"given":"Mahesh","family":"Mehendale","sequence":"additional","affiliation":[{"name":"Texas Instruments (India) Pvt Ltd, Bangalore, India"}]},{"given":"R.","family":"Govindarajan","sequence":"additional","affiliation":[{"name":"Indian Institute of Science, Bangalore, India"}]}],"member":"320","published-online":{"date-parts":[[2012,6,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2008.53"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735970.1736045"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360134"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771791"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1643608"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508269"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815983"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077696"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555758"},{"key":"e_1_3_2_1_15_1","volume-title":"DRAM Caching Dept of CS and Engg","author":"Wong W.","year":"1997","unstructured":"W. Wong and J-L Baer . DRAM Caching Dept of CS and Engg ., University of Washington Tech report UW-CSE-97-03-04 . 1997 . W. Wong and J-L Baer. DRAM Caching Dept of CS and Engg., University of Washington Tech report UW-CSE-97-03-04. 1997."},{"key":"e_1_3_2_1_16_1","unstructured":"The JEDEC consortium. www.jedec.org.  The JEDEC consortium. www.jedec.org."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_18_1","unstructured":"Micron. http:\/\/download.micron.com\/downloads\/misc\/ddr3_power_calc.xls.  Micron. http:\/\/download.micron.com\/downloads\/misc\/ddr3_power_calc.xls."},{"key":"e_1_3_2_1_19_1","unstructured":"Micron. Calculating Memory System Power for DDR3 http:\/\/download.micron.com\/pdf\/technotes\/ddr3\/TN41_01DDR3%20Power.pdf.  Micron. Calculating Memory System Power for DDR3 http:\/\/download.micron.com\/pdf\/technotes\/ddr3\/TN41_01DDR3%20Power.pdf."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/384264.379244"},{"key":"e_1_3_2_1_21_1","volume-title":"ISPASS","author":"Luo K.","year":"2001","unstructured":"K. Luo , J. Gummaraju , and M. Franklin . Balancing thoughput and fairness in smt processors . In ISPASS 2001 . K. Luo, J. Gummaraju, and M. Franklin. Balancing thoughput and fairness in smt processors. In ISPASS 2001."},{"key":"e_1_3_2_1_22_1","unstructured":"The SPEC Consortium. www.spec.org\/consortium\/  The SPEC Consortium. www.spec.org\/consortium\/"},{"key":"e_1_3_2_1_23_1","volume-title":"Number 6483769.","author":"La O.","year":"2002","unstructured":"O. La . SDRAM having posted CAS function of JEDEC standard. United States Patent , Number 6483769. 2002 . O. La. SDRAM having posted CAS function of JEDEC standard. United States Patent, Number 6483769. 2002."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382172"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000100"},{"key":"e_1_3_2_1_26_1","volume-title":"CACTI 5.0. Technical report. HP Laboratories","author":"Thoziyoor S.","year":"2007","unstructured":"S. Thoziyoor , N. Muralimanohar , and N. Jouppi . CACTI 5.0. Technical report. HP Laboratories 2007 . S. Thoziyoor, N. Muralimanohar, and N. Jouppi. CACTI 5.0. Technical report. HP Laboratories 2007."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"K. Itoh. VLSI Memory Chip Design. Springer 2001.  K. Itoh. VLSI Memory Chip Design. Springer 2001.","DOI":"10.1007\/978-3-662-04478-0"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.22"}],"event":{"name":"ICS'12: International Conference on Supercomputing","location":"San Servolo Island, Venice Italy","acronym":"ICS'12","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 26th ACM international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304613","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2304576.2304613","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:47Z","timestamp":1750236527000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2304576.2304613"}},"subtitle":["unlocking performance and energy improvement opportunities"],"short-title":[],"issued":{"date-parts":[[2012,6,25]]},"references-count":29,"alternative-id":["10.1145\/2304576.2304613","10.1145\/2304576"],"URL":"https:\/\/doi.org\/10.1145\/2304576.2304613","relation":{},"subject":[],"published":{"date-parts":[[2012,6,25]]},"assertion":[{"value":"2012-06-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}