{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,6]],"date-time":"2026-02-06T03:38:07Z","timestamp":1770349087979,"version":"3.49.0"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T00:00:00Z","timestamp":1343779200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CCF-0845751CCF-0917238CNS-0917213"],"award-info":[{"award-number":["CCF-0845751CCF-0917238CNS-0917213"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0845751CCF-0917238CNS-0917213"],"award-info":[{"award-number":["CCF-0845751CCF-0917238CNS-0917213"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Comput. Syst."],"published-print":{"date-parts":[[2012,8]]},"abstract":"<jats:p>Since 2004, processor designers have increased core counts to exploit Moore\u2019s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model single-core scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area\/performance and power\/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lower-bound core power. The multicore designs we study include single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9\u00d7 average speedup is possible across commonly used parallel workloads for the topologies we study, leaving a nearly 24-fold gap from a target of doubled performance per generation.<\/jats:p>","DOI":"10.1145\/2324876.2324879","type":"journal-article","created":{"date-parts":[[2012,8,21]],"date-time":"2012-08-21T13:06:30Z","timestamp":1345554390000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["Power Limitations and Dark Silicon Challenge the Future of Multicore"],"prefix":"10.1145","volume":"30","author":[{"given":"Hadi","family":"Esmaeilzadeh","sequence":"first","affiliation":[{"name":"University of Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emily","family":"Blem","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ren\u00e9e","family":"St. Amant","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthikeyan","family":"Sankaralingam","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[{"name":"Microsoft Research"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815967"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).","author":"Bakhoda A.","unstructured":"Bakhoda , A. , Yuan , G. L. , Fung , W. W. L. , Wong , H. , and Aamodt , T. M . 2009. Analyzing CUDA workloads using a detailed GPU simulator . In Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Bakhoda, A., Yuan, G. L., Fung, W. W. L., Wong, H., and Aamodt, T. M. 2009. Analyzing CUDA workloads using a detailed GPU simulator. In Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306793"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2010.5496640"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.18"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.36"},{"key":"e_1_2_1_10_1","volume-title":"Design of ion-implanted mosfet\u2019s with very small physical dimensions","author":"Dennard R. H.","unstructured":"Dennard , R. H. , Gaensslen , F. H. , Rideout , V. L. , Bassous , E. , and LeBlanc , A. R. 1974. Design of ion-implanted mosfet\u2019s with very small physical dimensions . IEEE J. Solid-State Circ . 9. Dennard, R. H., Gaensslen, F. H., Rideout, V. L., Bassous, E., and LeBlanc, A. R. 1974. Design of ion-implanted mosfet\u2019s with very small physical dimensions. IEEE J. Solid-State Circ. 9."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2007.02.004"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950402"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.4"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of MoBS.","author":"Hempstead M.","unstructured":"Hempstead , M. , Wei , G.-Y. , and Brooks , D . 2009. Navigo: An early-stage model to study power-contrained architectures and specialization . In Proceedings of MoBS. Hempstead, M., Wei, G.-Y., and Brooks, D. 2009. Navigo: An early-stage model to study power-contrained architectures and specialization. In Proceedings of MoBS."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 2005 International Electron Devices Meeting (IEDM).","author":"Horowitz M.","unstructured":"Horowitz , M. , Alon , E. , Patil , D. , Naffziger , S. , Kumar , R. , and Bernstein , K . 2005. Scaling, power, and the future of CMOS . In Proceedings of the 2005 International Electron Devices Meeting (IEDM). Horowitz, M., Alon, E., Patil, D., Naffziger, S., Kumar, R., and Bernstein, K. 2005. Scaling, power, and the future of CMOS. In Proceedings of the 2005 International Electron Devices Meeting (IEDM)."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"key":"e_1_2_1_19_1","volume-title":"International technology roadmap for semiconductors","year":"2010","unstructured":"ITRS. 2011. International technology roadmap for semiconductors , 2010 update. ITRS. 2011. International technology roadmap for semiconductors, 2010 update."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331733"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-92295-7_13"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816021"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the Workshop on Architectures and Languages for Troughput Applications (ALTA).","author":"Loh G.","year":"2008","unstructured":"Loh , G. 2008 . The cost of uncore in throughput-oriented many-core processors . In Proceedings of the Workshop on Architectures and Languages for Troughput Applications (ALTA). Loh, G. 2008. The cost of uncore in throughput-oriented many-core processors. In Proceedings of the Workshop on Architectures and Languages for Troughput Applications (ALTA)."},{"key":"e_1_2_1_24_1","first-page":"8","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"Moore G. E.","year":"1965","unstructured":"Moore , G. E. 1965 . Cramming more components onto integrated circuits . Electronics 38 , 8 . Moore, G. E. 1965. Cramming more components onto integrated circuits. Electronics 38, 8.","journal-title":"Electronics"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368755"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of MICRO.","author":"Pollack F.","year":"1999","unstructured":"Pollack , F. 1999 . New microarchitecture challenges in the coming generations of CMOS process technologies . In Proceedings of MICRO. Pollack, F. 1999. New microarchitecture challenges in the coming generations of CMOS process technologies. In Proceedings of MICRO."},{"key":"e_1_2_1_27_1","unstructured":"SPEC. 2011. Standard performance evaluation corporation. SPEC . 2011. Standard performance evaluation corporation."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.494"}],"container-title":["ACM Transactions on Computer Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2324876.2324879","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2324876.2324879","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:10Z","timestamp":1750243930000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2324876.2324879"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":29,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2012,8]]}},"alternative-id":["10.1145\/2324876.2324879"],"URL":"https:\/\/doi.org\/10.1145\/2324876.2324879","relation":{},"ISSN":["0734-2071","1557-7333"],"issn-type":[{"value":"0734-2071","type":"print"},{"value":"1557-7333","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8]]},"assertion":[{"value":"2012-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-08-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}