{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:04:38Z","timestamp":1774631078280,"version":"3.50.1"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"S2","license":[{"start":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T00:00:00Z","timestamp":1343779200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2012,8]]},"abstract":"<jats:p>We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator is calibrated based on a careful study of existing system-on-chip circuits. We show that our benchmark circuits lead to more realistic architectural conclusions than circuits generated using previous generators.<\/jats:p>","DOI":"10.1145\/2331147.2331152","type":"journal-article","created":{"date-parts":[[2012,9,11]],"date-time":"2012-09-11T22:21:06Z","timestamp":1347402066000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation"],"prefix":"10.1145","volume":"11","author":[{"given":"Cindy","family":"Mark","sequence":"first","affiliation":[{"name":"University of British Columbia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott Y. L.","family":"Chin","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lesley","family":"Shannon","sequence":"additional","affiliation":[{"name":"Simon Fraser University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2008. Avalon Interface Specifications. Manual MNL-AVABUSREF-2.0. Altera . 2008. Avalon Interface Specifications. Manual MNL-AVABUSREF-2.0."},{"key":"e_1_2_1_3_1","unstructured":"ARM. 2001. Amba Specification. Manual ARM IHI 0011A. ARM . 2001. Amba Specification. Manual ARM IHI 0011A."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/647924.738755"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs . Kluwer Academic Publishers.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (ICFPT). 1--8.","author":"Chin S. Y. L.","unstructured":"Chin , S. Y. L. and Wilton , S. J. E. 2007. Memory footprint reduction for FPGA routing algorithms . In Proceedings of the International Conference on Field-Programmable Technology (ICFPT). 1--8. Chin, S. Y. L. and Wilton, S. J. E. 2007. Memory footprint reduction for FPGA routing algorithms. In Proceedings of the International Conference on Field-Programmable Technology (ICFPT). 1--8."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.902258"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL). 205--211","author":"Das J.","unstructured":"Das , J. , Wilton , S. J. , Leong , P. , and Luk , W . 2009. Modeling post-techmapping and post-clustering FPGA circuit depth . In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL). 205--211 . Das, J., Wilton, S. J., Leong, P., and Luk, W. 2009. Modeling post-techmapping and post-clustering FPGA circuit depth. In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL). 205--211."},{"key":"e_1_2_1_9_1","unstructured":"eASIC. 2008. ePrize1. http:\/\/code.google.com\/p\/eprize1\/. eASIC . 2008. ePrize1. http:\/\/code.google.com\/p\/eprize1\/."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344694"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the Conference on Design Automation and Test in Europe. 656--663","author":"Ghosh D.","unstructured":"Ghosh , D. , Kapur , N. , Harlow , J. , and Brglez , F . 1998. Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking . In Proceedings of the Conference on Design Automation and Test in Europe. 656--663 . Ghosh, D., Kapur, N., Harlow, J., and Brglez, F. 1998. Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking. In Proceedings of the Conference on Design Automation and Test in Europe. 656--663."},{"key":"e_1_2_1_12_1","unstructured":"Gladston S. Hoffman B. and Gregoire N. 2001. SXP (Simple eXtensible Pipeline) Processor. http:\/\/opencores.org\/project.exp. Gladston S. Hoffman B. and Gregoire N. 2001. SXP (Simple eXtensible Pipeline) Processor. http:\/\/opencores.org\/project.exp."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391732.1391736"},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Harlow J. and Brglez F. 1997. Synthesis of ESI equivalence class combinational circuit mutants. Tech. rep. 1997-TR@CBL-07-Harlow North Carolina State University. http:\/\/www.cbl.ncsu.edu\/publications. Harlow J. and Brglez F. 1997. Synthesis of ESI equivalence class combinational circuit mutants. Tech. rep. 1997-TR@CBL-07-Harlow North Carolina State University. http:\/\/www.cbl.ncsu.edu\/publications.","DOI":"10.21236\/ADA344593"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.728919"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.800456"},{"key":"e_1_2_1_17_1","unstructured":"Karypis G. and Kumar V. 1999. Multilevel k-way hypergraph partitioning. Tech. rep. 98-036 University of Minnesota. Karypis G. and Kumar V. 1999. Multilevel k-way hypergraph partitioning. Tech. rep. 98-036 University of Minnesota."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828132"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344695"},{"key":"e_1_2_1_20_1","unstructured":"Lupas O. 2004. Serial UART. http:\/\/opencores.org\/project.uart. Lupas O. 2004. Serial UART. http:\/\/opencores.org\/project.uart."},{"key":"e_1_2_1_21_1","unstructured":"Marinissen E. J. Iyengar V. and Chakrabarty K. 2007. ITC\u201902 SOC test benchmarks. http:\/\/www.hitech-projects.com\/itc02socbenchm\/. Marinissen E. J. Iyengar V. and Chakrabarty K. 2007. ITC\u201902 SOC test benchmarks. http:\/\/www.hitech-projects.com\/itc02socbenchm\/."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (ICFPT\u201908)","author":"Mark C.","unstructured":"Mark , C. , Shui , A. , and Wilton , S. J. E. 2008. A system-level stochastic circuit generator for FPGA architecture evaluation . In Proceedings of the International Conference on Field-Programmable Technology (ICFPT\u201908) . 25--32. Mark, C., Shui, A., and Wilton, S. J. E. 2008. A system-level stochastic circuit generator for FPGA architecture evaluation. In Proceedings of the International Conference on Field-Programmable Technology (ICFPT\u201908). 25--32."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.892855"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.863641"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the International Conference on Field-Programmable Logic and Applications.","author":"Trimberger S.","year":"2007","unstructured":"Trimberger , S. 2007 . Keynote talk: Redefining the FPGA . In Proceedings of the International Conference on Field-Programmable Logic and Applications. Trimberger, S. 2007. Keynote talk: Redefining the FPGA. In Proceedings of the International Conference on Field-Programmable Logic and Applications."},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 213--216","author":"Verplaetse P.","unstructured":"Verplaetse , P. , Campenhout , J. V. , and Stroobandt , D . 2000. On synthetic benchmark generation methods . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 213--216 . Verplaetse, P., Campenhout, J. V., and Stroobandt, D. 2000. On synthetic benchmark generation methods. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 213--216."},{"key":"e_1_2_1_29_1","unstructured":"Xilinx. 2006. Virtex-5 family review. Data Sheet DS100. Xilinx . 2006. Virtex-5 family review. Data Sheet DS100."},{"key":"e_1_2_1_30_1","unstructured":"Yang S. 1991. Logic Synthesis and Optimization Benchmarks User Guide Versions 3.0. http:\/\/books.google.ca\/books?id=7ruGuAAACAAJ. Yang S. 1991. Logic Synthesis and Optimization Benchmarks User Guide Versions 3.0. http:\/\/books.google.ca\/books?id=7ruGuAAACAAJ."},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the Custom Integrated Circuits Conference (CICC). 93--96","author":"Zarkesh-Ha P.","unstructured":"Zarkesh-Ha , P. , Davis , J. A. , Loh , W. , and Meindl , J. D . 1998. On a pin versus gate relationship for heterogeneous systems: Heterogeneous Rent\u2019s rule . In Proceedings of the Custom Integrated Circuits Conference (CICC). 93--96 . Zarkesh-Ha, P., Davis, J. A., Loh, W., and Meindl, J. D. 1998. On a pin versus gate relationship for heterogeneous systems: Heterogeneous Rent\u2019s rule. In Proceedings of the Custom Integrated Circuits Conference (CICC). 93--96."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2331147.2331152","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2331147.2331152","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:49:12Z","timestamp":1750236552000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2331147.2331152"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":29,"journal-issue":{"issue":"S2","published-print":{"date-parts":[[2012,8]]}},"alternative-id":["10.1145\/2331147.2331152"],"URL":"https:\/\/doi.org\/10.1145\/2331147.2331152","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8]]},"assertion":[{"value":"2009-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-08-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}