{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T06:07:04Z","timestamp":1775455624991,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,7,30]],"date-time":"2012-07-30T00:00:00Z","timestamp":1343606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,7,30]]},"DOI":"10.1145\/2333660.2333666","type":"proceedings-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T13:43:14Z","timestamp":1343742194000},"page":"15-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["Design benchmarking to 7nm with FinFET predictive technology models"],"prefix":"10.1145","author":[{"given":"Saurabh","family":"Sinha","sequence":"first","affiliation":[{"name":"ARM Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brian","family":"Cline","sequence":"additional","affiliation":[{"name":"ARM Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Yeric","sequence":"additional","affiliation":[{"name":"ARM Inc., Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vikas","family":"Chandra","sequence":"additional","affiliation":[{"name":"ARM Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Cao","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,7,30]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE Custom Integrated Circuits Conf. (CICC)","author":"Li X.","year":"2009","unstructured":"X. Li , Y. Cao , Z. Zhu , J. Song , CMOS Designs using Predictive Technology Models\" , IEEE Custom Integrated Circuits Conf. (CICC) , 2009 , pp, 227--230. X. Li, Y. Cao, Z. Zhu, J. Song, et al. \"Pathfinding for 22nm CMOS Designs using Predictive Technology Models\", IEEE Custom Integrated Circuits Conf. (CICC), 2009, pp, 227--230."},{"key":"e_1_3_2_1_2_1","unstructured":"International Technology Roadmap for Semiconductors (ITRS) 2011 Edition www.itrs.net.  International Technology Roadmap for Semiconductors (ITRS) 2011 Edition www.itrs.net."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"e_1_3_2_1_4_1","volume-title":"Arizona State University","unstructured":"Predictive Technology Models , Arizona State University , Nanoscale Integration and Modeling Group . http:\/\/ptm.asu.edu\/latest.html. Predictive Technology Models, Arizona State University, Nanoscale Integration and Modeling Group. http:\/\/ptm.asu.edu\/latest.html."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2010573"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026519"},{"key":"e_1_3_2_1_7_1","first-page":"60","volume-title":"BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,\" in 2007 Symposium on VLSI Technology Digest of Technical Papers","author":"Dunga M. V.","year":"2007","unstructured":"M. V. Dunga , C.-H. Lin , D. D. Lu , W. Xiong , C. R. Cleavelin , P. Patruno , J.-R. Hwang , F.-L. Yang , A. M. Niknejad , and C. Hu , \" BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,\" in 2007 Symposium on VLSI Technology Digest of Technical Papers , 2007 , pp. 60 -- 61 . M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Hwang, F.-L. Yang, A. M. Niknejad, and C. Hu, \"BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,\" in 2007 Symposium on VLSI Technology Digest of Technical Papers, 2007, pp. 60--61."},{"key":"e_1_3_2_1_8_1","first-page":"34.1.1","volume-title":"A low operating power finfet transistor module featuring scaled gate stack and strain engineering for 32\/28nm soc technology,\" in IEDM, dec","author":"Yeh C.-C.","year":"2010","unstructured":"C.-C. Yeh , \" A low operating power finfet transistor module featuring scaled gate stack and strain engineering for 32\/28nm soc technology,\" in IEDM, dec . 2010 , pp. 34.1.1 -- 34.1.4 . C.-C. Yeh et al., \"A low operating power finfet transistor module featuring scaled gate stack and strain engineering for 32\/28nm soc technology,\" in IEDM, dec. 2010, pp. 34.1.1--34.1.4."},{"key":"e_1_3_2_1_9_1","first-page":"1","volume-title":"A 25-nm gate-length finfet transistor module for 32nm node,\" in IEDM, dec","author":"Chang C.-Y.","year":"2009","unstructured":"C.-Y. Chang , \" A 25-nm gate-length finfet transistor module for 32nm node,\" in IEDM, dec . 2009 , pp. 1 -- 4 . C.-Y. Chang et al., \"A 25-nm gate-length finfet transistor module for 32nm node,\" in IEDM, dec. 2009, pp. 1--4."},{"key":"e_1_3_2_1_10_1","first-page":"99","volume-title":"2011 International Conference on , vol., no.","year":"2011","unstructured":"Scholze, A.; Furkay, S.; Seong-Dong, Kim; Jain, S.; \"Exploring MOL design options for a 20nm CMOS technology using TCAD,\" Simulation of Semiconductor Processes and Devices (SISPAD) , 2011 International Conference on , vol., no. , pp. 99 -- 102 , 8-10 Sept. 2011 Scholze, A.; Furkay, S.; Seong-Dong, Kim; Jain, S.; \"Exploring MOL design options for a 20nm CMOS technology using TCAD,\" Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on , vol., no., pp. 99--102, 8-10 Sept. 2011"},{"key":"e_1_3_2_1_11_1","first-page":"36","volume-title":"IEEE Symp. VLSI Technology (VLSIT)","author":"Seo S.-C.","year":"2011","unstructured":"S.-C. Seo , L. F. Edge , S. Kanakasabapathy , M. Frank , 14 nm and Beyond \", IEEE Symp. VLSI Technology (VLSIT) , 2011 , pp. 36 -- 37 . S.-C. Seo, L. F. Edge, S. Kanakasabapathy, M. Frank, et al., \"Full Metal Gate with Borderless Contact for 14 nm and Beyond\", IEEE Symp. VLSI Technology (VLSIT), 2011, pp. 36--37."},{"key":"e_1_3_2_1_12_1","volume-title":"Digest of Technical Papers. 2006 Symposium on.","author":"Technology VLSI","year":"2006","unstructured":"Topol, A., et.al, \"Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS,\" VLSI Technology , 2006 . Digest of Technical Papers. 2006 Symposium on. Topol, A., et.al, \"Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS,\" VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on."},{"key":"e_1_3_2_1_13_1","first-page":"1","volume-title":"Review of finfet technology,\" in SOI Conference, oct","author":"Jurczak M.","year":"2009","unstructured":"M. Jurczak , \" Review of finfet technology,\" in SOI Conference, oct . 2009 , pp. 1 -- 4 . M. Jurczak et al., \"Review of finfet technology,\" in SOI Conference, oct. 2009, pp. 1--4."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339745"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2006.882565"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346871"},{"key":"e_1_3_2_1_17_1","first-page":"15.4.1","volume-title":"IEEE Intl. Electron Devices Meeting (IEDM)","author":"Yeric G.","year":"2011","unstructured":"G. Yeric , \"Technology Roadmaps and Low Power So C Design\" , IEEE Intl. Electron Devices Meeting (IEDM) , 2011 , pp. 15.4.1 -- 15.4.4 . G. Yeric, \"Technology Roadmaps and Low Power SoC Design\", IEEE Intl. Electron Devices Meeting (IEDM), 2011, pp. 15.4.1--15.4.4."},{"key":"e_1_3_2_1_18_1","first-page":"255","volume-title":"IEEE Intl. Conf. Nanotechnology","author":"Park C.-H.","year":"2011","unstructured":"C.-H. Park , S.-H. Lee , Y.-R. Kim , C.-K. Baek and Y.-H. Jeong , \"Gate-All-Around Silicon Nanowire Field Effect Transistors\" , IEEE Intl. Conf. Nanotechnology , 2011 , pp. 255 -- 259 . C.-H. Park, S.-H. Lee, Y.-R. Kim, C.-K. Baek and Y.-H. Jeong, \"Gate-All-Around Silicon Nanowire Field Effect Transistors\", IEEE Intl. Conf. Nanotechnology, 2011, pp. 255--259."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"}],"event":{"name":"ISLPED'12: International Symposium on Low Power Electronics and Design","location":"Redondo Beach California USA","acronym":"ISLPED'12","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"]},"container-title":["Proceedings of the 2012 ACM\/IEEE international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333666","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2333660.2333666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:21:06Z","timestamp":1750238466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333666"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,30]]},"references-count":19,"alternative-id":["10.1145\/2333660.2333666","10.1145\/2333660"],"URL":"https:\/\/doi.org\/10.1145\/2333660.2333666","relation":{},"subject":[],"published":{"date-parts":[[2012,7,30]]},"assertion":[{"value":"2012-07-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}