{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:24:11Z","timestamp":1750307051369,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,7,30]],"date-time":"2012-07-30T00:00:00Z","timestamp":1343606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,7,30]]},"DOI":"10.1145\/2333660.2333683","type":"proceedings-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T13:43:14Z","timestamp":1343742194000},"page":"85-90","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A 40-nm 256-Kb Sub-10 pJ\/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme"],"prefix":"10.1145","author":[{"given":"Shusuke","family":"Yoshimoto","sequence":"first","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaharu","family":"Terada","sequence":"additional","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youhei","family":"Umeki","sequence":"additional","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shunsuke","family":"Okumura","sequence":"additional","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Atsushi","family":"Kawasumi","sequence":"additional","affiliation":[{"name":"Semiconductor Technology Academic Research Center, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshikazu","family":"Suzuki","sequence":"additional","affiliation":[{"name":"Semiconductor Technology Academic Research Center, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinichi","family":"Moriwaki","sequence":"additional","affiliation":[{"name":"Semiconductor Technology Academic Research Center, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinji","family":"Miyano","sequence":"additional","affiliation":[{"name":"Semiconductor Technology Academic Research Center, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"Kawaguchi","sequence":"additional","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiko","family":"Yoshimoto","sequence":"additional","affiliation":[{"name":"Kobe University, Kobe, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,7,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382599"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Y. Morita K. Nose K. Noguchi S. Takami K. Goto Y. Aimoto A. Kimura and M. Mizuno \"Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme \" Digest of Technical Papers 2010 Symposium on VLSI Circuits pp. 37--38 Jun. 2010. Y. Morita K. Nose K. Noguchi S. Takami K. Goto Y. Aimoto A. Kimura and M. Mizuno \"Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme \" Digest of Technical Papers 2010 Symposium on VLSI Circuits pp. 37--38 Jun. 2010.","DOI":"10.1109\/VLSIC.2010.5560264"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"H. Pilo J. Barwin G. Braceras C. Browning S. Burns J. Gabric S. Lamphier and M. Miller \"An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage \" IEEE Symposium on VLSI Circuits pp. 15--16 June 2006. H. Pilo J. Barwin G. Braceras C. Browning S. Burns J. Gabric S. Lamphier and M. Miller \"An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage \" IEEE Symposium on VLSI Circuits pp. 15--16 June 2006.","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"K. Takeda T. Saito S. Asayama Y. Aimoto H. Kobatake S. Ito T. Takahashi K. Takeuchi M. Nomura and Y. Hayashi \"Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs \" Digest of Technical Papers 2010 Symposium on VLSI Circuits pp. 101--102 Jun. 2010. K. Takeda T. Saito S. Asayama Y. Aimoto H. Kobatake S. Ito T. Takahashi K. Takeuchi M. Nomura and Y. Hayashi \"Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs \" Digest of Technical Papers 2010 Symposium on VLSI Circuits pp. 101--102 Jun. 2010.","DOI":"10.1109\/VLSIC.2010.5560336"},{"key":"e_1_3_2_1_6_1","first-page":"348","volume-title":"IEEE International Solid-State Circuits Conference","author":"Fujimura Y.","year":"2010"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"H. Nho P. Kolar F. Hamzaoglu Y. Wang E. Karl Y. G. Ng U. Bhattacharya and K. Zhang \"A 32nm High-\u03ba Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation \" IEEE International Solid-State Circuits Conference pp. 346--347 2010. H. Nho P. Kolar F. Hamzaoglu Y. Wang E. Karl Y. G. Ng U. Bhattacharya and K. Zhang \"A 32nm High-\u03ba Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation \" IEEE International Solid-State Circuits Conference pp. 346--347 2010.","DOI":"10.1109\/ISSCC.2010.5433816"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Y. Morita H. Fujiwara H. Noguchi Y. Iguchi K. Nii H. Kawaguchi and M. Yoshimoto \"An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment \" IEEE Symposium on VLSI Circuits Digest of Technical Papers pp. 256--257 Jun. 2007. Y. Morita H. Fujiwara H. Noguchi Y. Iguchi K. Nii H. Kawaguchi and M. Yoshimoto \"An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment \" IEEE Symposium on VLSI Circuits Digest of Technical Papers pp. 256--257 Jun. 2007.","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"e_1_3_2_1_9_1","first-page":"625","author":"Pu Y.","year":"2010","journal-title":"of International Conference on Computer Aided Design"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"A. Kawasumi T. Suzuki S. Moriwaki and S. Miyano \"Energy Efficiency Degradation Caused by Random Variation in Low-Voltage SRAM and 26% Improvement by Bitline Amplitude Limiting (BAL) Scheme \" IEEE Asian Solid-State Circuits Conference pp. 165--168 Sep. 2011. A. Kawasumi T. Suzuki S. Moriwaki and S. Miyano \"Energy Efficiency Degradation Caused by Random Variation in Low-Voltage SRAM and 26% Improvement by Bitline Amplitude Limiting (BAL) Scheme \" IEEE Asian Solid-State Circuits Conference pp. 165--168 Sep. 2011.","DOI":"10.1109\/ASSCC.2011.6123628"},{"key":"e_1_3_2_1_11_1","unstructured":"S. Yoshimoto M. Terada S. Okumura T. Suzuki S. Miyano H. Kawaguchi and M. Yoshimoto \"A 40-nm 0.5-V 20.1-uW\/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme \" Digest of Technical Papers 2011 Symposium on VLSI Circuits pp. 72--73 Jun. 2011. S. Yoshimoto M. Terada S. Okumura T. Suzuki S. Miyano H. Kawaguchi and M. Yoshimoto \"A 40-nm 0.5-V 20.1-uW\/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme \" Digest of Technical Papers 2011 Symposium on VLSI Circuits pp. 72--73 Jun. 2011."}],"event":{"name":"ISLPED'12: International Symposium on Low Power Electronics and Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"],"location":"Redondo Beach California USA","acronym":"ISLPED'12"},"container-title":["Proceedings of the 2012 ACM\/IEEE international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333683","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2333660.2333683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:21:06Z","timestamp":1750238466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333683"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,30]]},"references-count":11,"alternative-id":["10.1145\/2333660.2333683","10.1145\/2333660"],"URL":"https:\/\/doi.org\/10.1145\/2333660.2333683","relation":{},"subject":[],"published":{"date-parts":[[2012,7,30]]},"assertion":[{"value":"2012-07-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}