{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:50Z","timestamp":1763468090357,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,7,30]],"date-time":"2012-07-30T00:00:00Z","timestamp":1343606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,7,30]]},"DOI":"10.1145\/2333660.2333718","type":"proceedings-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T13:43:14Z","timestamp":1343742194000},"page":"243-248","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Design space exploration of workload-specific last-level caches"],"prefix":"10.1145","author":[{"given":"Karthik","family":"Swaminathan","sequence":"first","affiliation":[{"name":"Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emre","family":"Kultursay","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vinay","family":"Saripalli","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmut","family":"Kandemir","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,7,30]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"ITRS","author":"Emerging Research ITRS","year":"2011","unstructured":"ITRS Emerging Research Devices (ERD) Chapter. In ITRS , 2011 . ITRS Emerging Research Devices (ERD) Chapter. In ITRS, 2011."},{"volume-title":"ITRS","year":"2011","key":"e_1_3_2_1_2_1","unstructured":"Process Integration , Devices, and Structures (PIDS) . In ITRS , 2011 . Process Integration, Devices, and Structures (PIDS). In ITRS, 2011."},{"key":"e_1_3_2_1_3_1","volume-title":"TCAD","author":"Dong X.","year":"2011","unstructured":"X. Dong : A Circuit-Level Performance, Energy, and Area Model for Emerging Non-Volatile Memory . In TCAD , Dec. 2011 . X. Dong et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-Volatile Memory. In TCAD, Dec. 2011."},{"key":"e_1_3_2_1_4_1","volume-title":"ISCA","author":"Flautner K.","year":"2002","unstructured":"K. Flautner Drowsy caches: simple techniques for reducing leakage power . In ISCA , 2002 . K. Flautner et al. Drowsy caches: simple techniques for reducing leakage power. In ISCA, 2002."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.15"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.909751"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSL.2003.821550"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266818"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283818"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000074"},{"key":"e_1_3_2_1_13_1","volume-title":"IEDM","author":"Mookerjea S.","year":"2009","unstructured":"S. Mookerjea Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications . In IEDM , 2009 . S. Mookerjea et al. Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. In IEDM, 2009."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"},{"issue":"8","key":"e_1_3_2_1_15_1","first-page":"847","article-title":"1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS","volume":"30","author":"Mutoh S.","year":"1995","unstructured":"S. Mutoh 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS . JSSC , 30 ( 8 ): 847 -- 854 , Aug 1995 . S. Mutoh et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. JSSC, 30(8):847--854, Aug 1995.","journal-title":"JSSC"},{"key":"e_1_3_2_1_16_1","volume-title":"ISQED","author":"Qin H.","year":"2004","unstructured":"H. Qin SRAM leakage suppression by minimizing standby supply voltage . In ISQED , 2004 . H. Qin et al. SRAM leakage suppression by minimizing standby supply voltage. In ISQED, 2004."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941482"},{"key":"e_1_3_2_1_18_1","volume-title":"EE Times","author":"Shifren L.","year":"2011","unstructured":"L. Shifren . Leakage power, it's worse than you think . In EE Times , 2011 . L. Shifren. Leakage power, it's worse than you think. In EE Times, 2011."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014861"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/2016802.2016859"},{"key":"e_1_3_2_1_21_1","first-page":"06","article-title":"TCAD Sentaurus Device Manual, Release","year":"2009","unstructured":"Synopsys . TCAD Sentaurus Device Manual, Release : C- 2009 . 06 , 2009. Synopsys. TCAD Sentaurus Device Manual, Release: C-2009.06, 2009.","journal-title":"C-"},{"key":"e_1_3_2_1_22_1","volume-title":"ICCD","author":"Wong W.","year":"2007","unstructured":"W. Wong : Voltage scaled cache hierarchies . In ICCD , 2007 . W. Wong et al. VOSCH: Voltage scaled cache hierarchies. In ICCD, 2007."},{"key":"e_1_3_2_1_23_1","volume-title":"ISSCC","author":"Zhai B.","year":"2007","unstructured":"B. Zhai A sub-200mV 6T-SRAM in 0.13um CMOS . In ISSCC , 2007 . B. Zhai et al. A sub-200mV 6T-SRAM in 0.13um CMOS. In ISSCC, 2007."}],"event":{"name":"ISLPED'12: International Symposium on Low Power Electronics and Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"],"location":"Redondo Beach California USA","acronym":"ISLPED'12"},"container-title":["Proceedings of the 2012 ACM\/IEEE international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333718","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2333660.2333718","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:21:06Z","timestamp":1750238466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2333660.2333718"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,30]]},"references-count":23,"alternative-id":["10.1145\/2333660.2333718","10.1145\/2333660"],"URL":"https:\/\/doi.org\/10.1145\/2333660.2333718","relation":{},"subject":[],"published":{"date-parts":[[2012,7,30]]},"assertion":[{"value":"2012-07-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}