{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:36:21Z","timestamp":1773246981188,"version":"3.50.1"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,9,1]],"date-time":"2012-09-01T00:00:00Z","timestamp":1346457600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2012,9]]},"abstract":"<jats:p>\n            Side-channel attacks in general and power analysis attacks in particular are becoming a major security concern in embedded systems. Countermeasures proposed against power analysis attacks are data and table masking, current flattening, dummy instruction insertion and bit-flips balancing. All these techniques are either susceptible to multi-order power analysis attack, not sufficiently generic to cover all encryption algorithms, or burden the system with high area, run-time or energy cost. In this article, we propose a randomized instruction injection technique (\n            <jats:italic>RIJID<\/jats:italic>\n            ) that overcomes the pitfalls of previous countermeasures.\n            <jats:italic>RIJID<\/jats:italic>\n            scrambles the power profile of a cryptographic application by injecting random instructions at random points of execution and therefore protects the system against power analysis attacks. Two different ways of triggering the instruction injection are also presented: (1)\n            <jats:italic>softRIJID<\/jats:italic>\n            , a hardware\/software approach, where special instructions are used in the code for triggering the injection at runtime; and (2)\n            <jats:italic>autoRIJID<\/jats:italic>\n            , a hardware approach, where the code injection is triggered by the processor itself via detecting signatures of encryption routines at runtime. A novel signature detection technique is also introduced for identifying encryption routines within application programs at runtime. Further, a simple obfuscation metric (\n            <jats:italic>RIJIDindex<\/jats:italic>\n            ) based on cross-correlation that measures the scrambling provided by any code injection technique is introduced, which coarsely indicates the level of scrambling achieved. Our processor models cost 1.9% additional area in the hardware\/software approach and 1.2% in the hardware approach for a\n            <jats:italic>RISC<\/jats:italic>\n            based processor, and costs on average 29.8% in runtime and 27.1% in energy for the former and 25.0% in runtime and 28.5% in energy for the later, for industry standard cryptographic applications.\n          <\/jats:p>","DOI":"10.1145\/2345770.2345782","type":"journal-article","created":{"date-parts":[[2012,10,2]],"date-time":"2012-10-02T13:50:00Z","timestamp":1349185800000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Randomized Instruction Injection to Counter Power Analysis Attacks"],"prefix":"10.1145","volume":"11","author":[{"given":"Jude A.","family":"Ambrose","sequence":"first","affiliation":[{"name":"University of New South Wales"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roshan G.","family":"Ragel","sequence":"additional","affiliation":[{"name":"University of Peradeniya"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[{"name":"University of New South Wales"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,9]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 6th International Conference on the Theory and Application of Cryptology and Information Security (ASIACRYPT\u201900)","author":"Akkar M.-L."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278606"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289832"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/11586821_16"},{"key":"e_1_2_1_5_1","volume-title":"N.","author":"Blake I.","year":"2005"},{"key":"e_1_2_1_6_1","first-page":"93","article-title":"GPU Gems 3 - Generic Adaptive Mesh Refinement. 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Resistance against implementation attacks: A comparative study of the AES proposals. http:\/\/csrc.nist.gov\/CryptoToolkit\/aes\/round1\/pubcmnts.htm."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878344"},{"key":"e_1_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Gebotys C. H. and Gebotys R. J. 2003. Secure elliptic curve implementations: An analysis of resistance to power-attacks in a DSP processor. In Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems (CHES\u201902). Springer 114--128. Gebotys C. H. and Gebotys R. J. 2003. Secure elliptic curve implementations: An analysis of resistance to power-attacks in a DSP processor. In Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems (CHES\u201902) . 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