{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:15Z","timestamp":1750308735676,"version":"3.41.0"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2012,10,1]],"date-time":"2012-10-01T00:00:00Z","timestamp":1349049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2012,10]]},"abstract":"<jats:p>We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.<\/jats:p>","DOI":"10.1145\/2348839.2348851","type":"journal-article","created":{"date-parts":[[2012,10,18]],"date-time":"2012-10-18T13:48:27Z","timestamp":1350568107000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults"],"prefix":"10.1145","volume":"17","author":[{"given":"Arijit","family":"Mondal","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. 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Fast test pattern generation for all path delay faults consideringvarious test classes . In Proceedings of the 3rd European Test Conference. 89--98 . Fuchs, K., Wittmann, H., and Antreich, K. 1993. Fast test pattern generation for all path delay faults consideringvarious test classes. In Proceedings of the 3rd European Test Conference. 89--98."},{"key":"e_1_2_1_6_1","volume-title":"RESIST: A recursive test pattern generation algorithm for path delay faults. In Proceedings of the Conference on European Design Automation","author":"Fuchs K.","year":"1994","unstructured":"Fuchs , K. , Pabst , M. , and R\u00f6ssel , T . 1994 . RESIST: A recursive test pattern generation algorithm for path delay faults. In Proceedings of the Conference on European Design Automation . IEEE Computer Society Press , 316--321. Fuchs, K., Pabst, M., and R\u00f6ssel, T. 1994. RESIST: A recursive test pattern generation algorithm for path delay faults. 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