{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:51:28Z","timestamp":1750308688993,"version":"3.41.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,9,1]],"date-time":"2012-09-01T00:00:00Z","timestamp":1346457600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2012,9]]},"abstract":"<jats:p>\n            With the continuing scaling of semiconductor technologies, chip multiprocessor (CMP) has become the de facto design for modern high performance computer architectures. It is expected that more and more applications with diverse requirements will run simultaneously on the CMP platform. However, this will exert contention on shared resources such as the last level cache, network-on-chip bandwidth and off-chip memory bandwidth, thus affecting the performance and quality-of-service (QoS) significantly. In this environment, efficient resource sharing and a guarantee of a certain level of performance is highly desirable. Researchers have proposed different frameworks for providing QoS. Most of these frameworks focus on individual resource for QoS management. Coordinated management of multiple QoS-aware shared resources at runtime remains an open problem. Recently, there has been work that proposed a class-of-serviced based framework to jointly managing cache, NoC and memory resources simultaneously. However, the work allocates shared resources\n            <jats:italic>statically<\/jats:italic>\n            at the beginning of application runtime, and do not dynamically track, manage and share shared resources across applications. In this article, we address this limitation by proposing dynamic resource management policies that monitor the resource usage of applications at runtime, then steals resources from the high-priority applications for lower-priority ones. The goal is to maintain the targeted level of performance for high-priority applications while improving the performance of lower-priority applications. We use a PI (Proportional-Integral gain) feedback controller based technique to maintain stability in our framework. Our evaluation results show that our policy can improve performance for lower-priority applications significantly while maintaining the performance for high-priority application, thus demonstrating the effectiveness of our dynamic QoS resource management policy.\n          <\/jats:p>","DOI":"10.1145\/2355585.2355590","type":"journal-article","created":{"date-parts":[[2012,10,2]],"date-time":"2012-10-02T13:50:00Z","timestamp":1349185800000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Dynamic QoS management for chip multiprocessors"],"prefix":"10.1145","volume":"9","author":[{"given":"Bin","family":"Li","sequence":"first","affiliation":[{"name":"Princeton University, Hillsboro, OR"}]},{"given":"Li-Shiuan","family":"Peh","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA"}]},{"given":"Li","family":"Zhao","sequence":"additional","affiliation":[{"name":"Intel Labs, Hillsboro, OR"}]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel Labs, Hillsboro, OR"}]}],"member":"320","published-online":{"date-parts":[[2012,10,5]]},"reference":[{"volume-title":"Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 33--42","author":"Agarwal N.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","unstructured":"Akesson B. 2010. Predictable and composable system-on-chip memory controllers. Ph.D. thesis Department of Electrical Engineering Eindhoven University of Technology.  Akesson B. 2010. Predictable and composable system-on-chip memory controllers. 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