{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:24:45Z","timestamp":1750307085580,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,10,1]],"date-time":"2012-10-01T00:00:00Z","timestamp":1349049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2012,10]]},"abstract":"<jats:p>Asymmetric coherency is a new optimization method for coherency policies to support nonuniform workloads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applicable to SoC multicores where the applications are not evenly spread among the processors and customization of the coherency is possible. Asymmetric coherency is a policy change, and consequently our designs require little or no additional hardware over an existing system. We explore two different types of asymmetric coherency policies. Our bus-based asymmetric coherency policy, generated a 60% coherency cost reduction (reduction of latencies due to coherency messages) for nonshared data. Our directory-based asymmetric coherency policy, showed up to a 5.8% execution time improvement and up to a 22% improvement in average memory latency for the parallel benchmarks Sha, using a statically allocated asymmetry. Dynamically allocated asymmetry was found to generate further improvements in access latency, increasing the effectiveness of asymmetric coherency by up to 73.8% when compared to the static asymmetric solution.<\/jats:p>","DOI":"10.1145\/2362374.2362376","type":"journal-article","created":{"date-parts":[[2012,10,18]],"date-time":"2012-10-18T13:23:19Z","timestamp":1350566599000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Asymmetric Cache Coherency"],"prefix":"10.1145","volume":"5","author":[{"given":"John","family":"Shield","sequence":"first","affiliation":[{"name":"Lab-STICC, Universit\u00e9 de Bretagne-Sud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Philippe","family":"Diguet","sequence":"additional","affiliation":[{"name":"Lab-STICC, Universit\u00e9 de Bretagne-Sud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guy","family":"Gogniat","sequence":"additional","affiliation":[{"name":"Lab-STICC, Universit\u00e9 de Bretagne-Sud"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,10]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1069995"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325124"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195501"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346210"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165146"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2010.14"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"volume-title":"Multiprocessor System-on-Chip: Hardware Design and Tool Integration","author":"Kumar R.","key":"e_1_2_1_10_1","unstructured":"Kumar , R. , Mattson , T. G. , Pokam , G. , and van der Wijngaar , R. 2011. A case for message passing for many-core computing . In Multiprocessor System-on-Chip: Hardware Design and Tool Integration . Springer . Kumar, R., Mattson, T. G., Pokam, G., and van der Wijngaar, R. 2011. A case for message passing for many-core computing. In Multiprocessor System-on-Chip: Hardware Design and Tool Integration. Springer."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859642"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"volume-title":"Proceedings of the 17th International Conference on Field Programmable Logic and Applications. IEEE, 625--628","author":"Shield J.","key":"e_1_2_1_13_1","unstructured":"Shield , J. , Sutton , P. , and Machanick , P . 2007. Analysis of kernel effects on optimisation mismatch in cache reconfiguration . In Proceedings of the 17th International Conference on Field Programmable Logic and Applications. IEEE, 625--628 . Shield, J., Sutton, P., and Machanick, P. 2007. Analysis of kernel effects on optimisation mismatch in cache reconfiguration. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications. IEEE, 625--628."},{"volume-title":"Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip. 1--8.","author":"Shield J.","key":"e_1_2_1_14_1","unstructured":"Shield , J. , Diguet , J.-P. , and Gogniat , G . 2011. Asymmetric cache coherency: Improving multicore performance for non-uniform workloads . In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip. 1--8. Shield, J., Diguet, J.-P., and Gogniat, G. 2011. Asymmetric cache coherency: Improving multicore performance for non-uniform workloads. In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip. 1--8."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165147"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923415"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2362374.2362376","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2362374.2362376","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:34:22Z","timestamp":1750239262000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2362374.2362376"}},"subtitle":["Policy Modifications to Improve Multicore Performance"],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":16,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2012,10]]}},"alternative-id":["10.1145\/2362374.2362376"],"URL":"https:\/\/doi.org\/10.1145\/2362374.2362376","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2012,10]]},"assertion":[{"value":"2011-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-10-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}