{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:03:53Z","timestamp":1761581033181,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2012,10,1]],"date-time":"2012-10-01T00:00:00Z","timestamp":1349049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001665","name":"Agence Nationale de la Recherche","doi-asserted-by":"publisher","award":["ANR-09-SEGI-013"],"award-info":[{"award-number":["ANR-09-SEGI-013"]}],"id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2012,10]]},"abstract":"<jats:p>In data security systems, general purpose processors (GPPs) are often extended by a cryptographic accelerator. The article presents three ways of extending GPPs for symmetric key cryptography applications. Proposed extensions guarantee secure key storage and management even if the system is facing protocol, software and cache memory attacks. The system is partitioned into processor, cipher, and key memory zones. The three security zones are separated at protocol, system, architecture and physical levels. The proposed principle was validated on Altera NIOS II, Xilinx MicroBlaze and Microsemi Cortex M1 soft-core processor extensions. We show that stringent separation of the cipher zone is helpful for partial reconfiguration of the security module, if the enciphering algorithm needs to be dynamically changed. However, the key zone including reconfiguration controller must remain static in order to maintain the high level of security required. We demonstrate that the principle is feasible in partially reconfigurable field programmable gate arrays (FPGAs) such as Altera Stratix V or Xilinx Virtex 6 and also to some extent in FPGAs featuring hardwired general purpose processors such as Cortex M3 in Microsemi SmartFusion FPGA. Although the three GPPs feature different data interfaces, we show that the processors with their extensions reach the required high security level while maintaining partial reconfiguration capability.<\/jats:p>","DOI":"10.1145\/2362374.2362380","type":"journal-article","created":{"date-parts":[[2012,10,18]],"date-time":"2012-10-18T13:23:19Z","timestamp":1350566599000},"page":"1-13","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities"],"prefix":"10.1145","volume":"5","author":[{"given":"Lubos","family":"Gaspar","sequence":"first","affiliation":[{"name":"Hubert Curien Laboratory, Jean Monnet University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Viktor","family":"Fischer","sequence":"additional","affiliation":[{"name":"Hubert Curien Laboratory, Jean Monnet University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lilian","family":"Bossuet","sequence":"additional","affiliation":[{"name":"Hubert Curien Laboratory, Jean Monnet University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Fouquet","sequence":"additional","affiliation":[{"name":"Hubert Curien Laboratory, Jean Monnet University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,10]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2010. 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Cache games--Bringing access-based cache attacks on AES to practice. In Proceedings of the Workshop on Constructive Side-Channel Analysis and Secure Design. 215--221."},{"volume-title":"Proceedings of the Reconfigurable Architectures Workshop (RAW). 146--154","author":"Bossuet L.","key":"e_1_2_1_6_1","unstructured":"Bossuet , L. , Gogniat , G. , and Burleson , W . 2004. Dynamically configurable security for sram FPGA bitstreams . In Proceedings of the Reconfigurable Architectures Workshop (RAW). 146--154 . Bossuet, L., Gogniat, G., and Burleson, W. 2004. Dynamically configurable security for sram FPGA bitstreams. In Proceedings of the Reconfigurable Architectures Workshop (RAW). 146--154."},{"volume-title":"Proceedings of the International Conference on Field Programmable Technology (FPT\u201904)","author":"Crowe F.","key":"e_1_2_1_7_1","unstructured":"Crowe , F. , Daly , A. , Kerins , T. , and Marnane , W . 2004. Single-chip FPGA implementation of a cryptographic co-processor . In Proceedings of the International Conference on Field Programmable Technology (FPT\u201904) . 279--285. Crowe, F., Daly, A., Kerins, T., and Marnane, W. 2004. Single-chip FPGA implementation of a cryptographic co-processor. In Proceedings of the International Conference on Field Programmable Technology (FPT\u201904). 279--285."},{"key":"e_1_2_1_8_1","unstructured":"Davies P. 2003. Flexibile security. Thales e-Security White Paper - Cryptography & Interoperability. Davies P. 2003. Flexibile security. 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In Proceedings of the International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip."},{"key":"e_1_2_1_14_1","first-page":"29","article-title":"Design and implementation of a private and public key crypto processor for next-generation it security applications","volume":"19","author":"Hani M.","year":"2006","unstructured":"Hani , M. , Wen , H. , and Paniandi , A. 2006 . Design and implementation of a private and public key crypto processor for next-generation it security applications . Malaysia J. Comput. Sci. 19 , 1, 29 -- 45 . Hani, M., Wen, H., and Paniandi, A. 2006. Design and implementation of a private and public key crypto processor for next-generation it security applications. Malaysia J. Comput. Sci. 19, 1, 29--45.","journal-title":"Malaysia J. Comput. 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