{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T03:16:56Z","timestamp":1782875816483,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,9,19]],"date-time":"2012-09-19T00:00:00Z","timestamp":1348012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,9,19]]},"DOI":"10.1145\/2370816.2370833","type":"proceedings-article","created":{"date-parts":[[2012,9,25]],"date-time":"2012-09-25T23:48:43Z","timestamp":1348616923000},"page":"107-116","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["Scalability-based manycore partitioning"],"prefix":"10.1145","author":[{"given":"Hiroshi","family":"Sasaki","sequence":"first","affiliation":[{"name":"Kyushu University, Fukuoka, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Teruo","family":"Tanimoto","sequence":"additional","affiliation":[{"name":"Fujitsu Laboratories Limited, Kawasaki, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koji","family":"Inoue","sequence":"additional","affiliation":[{"name":"Kyushu University, Fukuoka, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hiroshi","family":"Nakamura","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2012,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/1413370.1413410"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810113"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1880018.1880019"},{"key":"e_1_3_2_1_6_1","volume-title":"USENIXATC '11","author":"Blagodurov S.","year":"2011","unstructured":"S. Blagodurov A case for NUMA-aware contention management on multicore systems . In USENIXATC '11 , 2011 . S. Blagodurov et al. A case for NUMA-aware contention management on multicore systems. In USENIXATC '11, 2011."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155641"},{"key":"e_1_3_2_1_8_1","volume-title":"OSDI '00","author":"Corbal\u00e1n J.","year":"2000","unstructured":"J. Corbal\u00e1n Performance-driven processor allocation . In OSDI '00 , 2000 . J. Corbal\u00e1n et al. Performance-driven processor allocation. In OSDI '00, 2000."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377852"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.85"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299108"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/46\/1\/067"},{"key":"e_1_3_2_1_14_1","volume-title":"Exploring the Design Space of Future CMPs. In PACT '01","author":"Huh J.","year":"2001","unstructured":"J. Huh Exploring the Design Space of Future CMPs. In PACT '01 , 2001 . J. Huh et al. Exploring the Design Space of Future CMPs. In PACT '01, 2001."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.48"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815996"},{"key":"e_1_3_2_1_17_1","first-page":"367","volume-title":"HPCA '08","author":"Lin J.","year":"2008","unstructured":"J. Lin Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems . In HPCA '08 , pages 367 -- 378 , 2008 . J. Lin et al. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In HPCA '08, pages 367--378, 2008."},{"key":"e_1_3_2_1_18_1","volume-title":"ISPASS '01","author":"Lun K.","year":"2001","unstructured":"K. Lun Balancing thoughput and fairness in SMT processors . In ISPASS '01 , 2001 . K. Lun et al. Balancing thoughput and fairness in SMT processors. In ISPASS '01, 2001."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993478.1993481"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1987816.1987832"},{"issue":"4","key":"e_1_3_2_1_21_1","article-title":"Intel\u00ae threading building blocks","volume":"23","author":"Pheatt C.","year":"2008","unstructured":"C. Pheatt . Intel\u00ae threading building blocks . Journal of Computing Sciences in Colleges , 23 ( 4 ), 2008 . C. Pheatt. Intel\u00ae threading building blocks. Journal of Computing Sciences in Colleges, 23(4), 2008.","journal-title":"Journal of Computing Sciences in Colleges"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2016604.2016647"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/645607.661687"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183450"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854307"}],"event":{"name":"PACT '12: International Conference on Parallel Architectures and Compilation Techniques","location":"Minneapolis Minnesota USA","acronym":"PACT '12","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"]},"container-title":["Proceedings of the 21st international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370833","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2370816.2370833","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:34:17Z","timestamp":1750239257000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370833"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9,19]]},"references-count":29,"alternative-id":["10.1145\/2370816.2370833","10.1145\/2370816"],"URL":"https:\/\/doi.org\/10.1145\/2370816.2370833","relation":{},"subject":[],"published":{"date-parts":[[2012,9,19]]},"assertion":[{"value":"2012-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}