{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:40Z","timestamp":1763468080262,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,9,19]],"date-time":"2012-09-19T00:00:00Z","timestamp":1348012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,9,19]]},"DOI":"10.1145\/2370816.2370836","type":"proceedings-article","created":{"date-parts":[[2012,9,25]],"date-time":"2012-09-25T23:48:43Z","timestamp":1348616923000},"page":"127-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":140,"title":["Evaluation of Blue Gene\/Q hardware support for transactional memories"],"prefix":"10.1145","author":[{"given":"Amy","family":"Wang","sequence":"first","affiliation":[{"name":"IBM Toronto Software Laboratory, Markham, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Gaudet","sequence":"additional","affiliation":[{"name":"University of Alberta, Edmonton, AB, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Wu","sequence":"additional","affiliation":[{"name":"IBM Research, Yorktown, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 Nelson","family":"Amaral","sequence":"additional","affiliation":[{"name":"University of Alberta, Edmonton, AB, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin","family":"Ohmacht","sequence":"additional","affiliation":[{"name":"IBM Research, Yorktown, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Barton","sequence":"additional","affiliation":[{"name":"IBM Toronto Software Laboratory, Markham, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raul","family":"Silvera","sequence":"additional","affiliation":[{"name":"IBM Toronto Software Laboratory, Markham, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maged","family":"Michael","sequence":"additional","affiliation":[{"name":"IBM Research, Yorktown, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1400214.1400228"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.40"},{"key":"e_1_3_2_1_5_1","volume-title":"HP Labs' Bay Area Workshop on Transactional Memory","author":"Click C.","year":"2009","unstructured":"C. Click . Azul's experiences with hardware transactional memory . In HP Labs' Bay Area Workshop on Transactional Memory , 2009 . C. Click. Azul's experiences with hardware transactional memory. In HP Labs' Bay Area Workshop on Transactional Memory, 2009."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555814"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693464"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508263"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.49"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345241"},{"key":"e_1_3_2_1_11_1","volume-title":"Draft specification of transactional language constructs for C++ (version 1.1)","author":"T. M. S. D. Group","year":"2012","unstructured":"T. M. S. D. Group . Draft specification of transactional language constructs for C++ (version 1.1) , 2012 . T. M. S. D. Group. Draft specification of transactional language constructs for C++ (version 1.1), 2012."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.108"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_14_1","volume-title":"February","author":"Intel Corporation","year":"2012","unstructured":"Intel Corporation . Intel Architecture Instruction Set Extensions Programming Reference, 319433-012 edition , February 2012 . Intel Corporation. Intel Architecture Instruction Set Extensions Programming Reference, 319433-012 edition, February 2012."},{"key":"e_1_3_2_1_15_1","unstructured":"D. Kanter. Analysis of Haswell's transactional memory. http:\/\/www.realworldtech.com\/page.cfm?ArticleID=RWT021512050738&p=1 February 2012. Real World Technologies.  D. Kanter. Analysis of Haswell's transactional memory. http:\/\/www.realworldtech.com\/page.cfm?ArticleID=RWT021512050738&p=1 February 2012. Real World Technologies."},{"key":"e_1_3_2_1_16_1","first-page":"35","volume-title":"International Symposium on Workload Characterization (IISWC)","author":"Minh C. C.","year":"2008","unstructured":"C. C. Minh , J. Chung , C. Kozyrakis , and K. Olukotun . STAMP: Stanford transactional applications for multi-processing . In International Symposium on Workload Characterization (IISWC) , pages 35 -- 46 , Seattle, WA, USA , September 2008 . C. C. Minh, J. Chung, C.Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In International Symposium on Workload Characterization (IISWC), pages 35--46, Seattle, WA, USA, September 2008."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250673"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1123001"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378583"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/88.260295"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.4"}],"event":{"name":"PACT '12: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"],"location":"Minneapolis Minnesota USA","acronym":"PACT '12"},"container-title":["Proceedings of the 21st international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370836","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2370816.2370836","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:34:17Z","timestamp":1750239257000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370836"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9,19]]},"references-count":21,"alternative-id":["10.1145\/2370816.2370836","10.1145\/2370816"],"URL":"https:\/\/doi.org\/10.1145\/2370816.2370836","relation":{},"subject":[],"published":{"date-parts":[[2012,9,19]]},"assertion":[{"value":"2012-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}