{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T01:42:58Z","timestamp":1787017378196,"version":"build-2736575974"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,9,19]],"date-time":"2012-09-19T00:00:00Z","timestamp":1348012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,9,19]]},"DOI":"10.1145\/2370816.2370873","type":"proceedings-article","created":{"date-parts":[[2012,9,25]],"date-time":"2012-09-25T19:48:43Z","timestamp":1348602523000},"page":"401-410","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["Workload and power budget partitioning for single-chip heterogeneous processors"],"prefix":"10.1145","author":[{"given":"Hao","family":"Wang","sequence":"first","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vijay","family":"Sathish","sequence":"additional","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ripudaman","family":"Singh","sequence":"additional","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael J.","family":"Schulte","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2012,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.41"},{"key":"e_1_3_2_1_3_1","unstructured":"NVIDIA. What is CUDA? {Online}. http:\/\/www.nvidia.com\/object\/cuda_home_new.html  NVIDIA. What is CUDA? {Online}. http:\/\/www.nvidia.com\/object\/cuda_home_new.html"},{"key":"e_1_3_2_1_4_1","unstructured":"OpenCL - The open standard for parallel programming of heterogeneous systems. {Online}. http:\/\/www.khronos.org\/opencl\/  OpenCL - The open standard for parallel programming of heterogeneous systems. {Online}. http:\/\/www.khronos.org\/opencl\/"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.2"},{"key":"e_1_3_2_1_6_1","first-page":"264","volume-title":"Solid-State Circuits Conf. (ISSCC)","author":"Yuffe M.","year":"2011","unstructured":"M. Yuffe , E. Knoll , M. Mehalel , J. Shor , and T. Kurts , \" A fully integrated multi-CPU, GPU and memory controller 32nm processor,\" in IEEE Int . Solid-State Circuits Conf. (ISSCC) , 2011 , pp. 264 -- 266 . M. Yuffe, E. Knoll, M. Mehalel, J. Shor, and T. Kurts, \"A fully integrated multi-CPU, GPU and memory controller 32nm processor,\" in IEEE Int. Solid-State Circuits Conf. (ISSCC) , 2011, pp. 264--266."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669121"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346318"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250753"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2010.22"},{"key":"e_1_3_2_1_11_1","volume-title":"AMD'S Llano Fusion APU,\" in IEEE\/ACM Symp. on High Performance Chips (HOTCHIPS)","author":"Foley D","year":"2011","unstructured":"D Foley , \" AMD'S Llano Fusion APU,\" in IEEE\/ACM Symp. on High Performance Chips (HOTCHIPS) , 2011 . D Foley et al., \"AMD'S Llano Fusion APU,\" in IEEE\/ACM Symp. on High Performance Chips (HOTCHIPS), 2011."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.17"},{"key":"e_1_3_2_1_14_1","first-page":"77","volume-title":"Symp. on High-Performance Computer Architecture (HPCA)","author":"Li J.","year":"2006","unstructured":"J. Li and J.F. Martinez , \" Dynamic power-performance adaptation of parallel computation on chip multiprocessors,\" in IEEE\/ACM Int . Symp. on High-Performance Computer Architecture (HPCA) , 2006 , pp. 77 -- 87 . J. Li and J.F. Martinez, \"Dynamic power-performance adaptation of parallel computation on chip multiprocessors,\" in IEEE\/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 2006, pp. 77--87."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_16_1","volume-title":"Analyzing CUDA Workloads using a Detailed GPU Simulator,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda , G. Yuan , W. W. L. Fung , H. Wong , and T. M. Aamodt , \" Analyzing CUDA Workloads using a Detailed GPU Simulator,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , 2009 . A. Bakhoda, G. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, \"Analyzing CUDA Workloads using a Detailed GPU Simulator,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2009."},{"key":"e_1_3_2_1_17_1","unstructured":"NVIDIA. GeForce GTS 260M Specification. {Online}. http:\/\/www.geforce.com\/hardware\/notebook-gpus\/geforce-gts-260m\/specifications  NVIDIA. GeForce GTS 260M Specification. {Online}. http:\/\/www.geforce.com\/hardware\/notebook-gpus\/geforce-gts-260m\/specifications"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"e_1_3_2_1_22_1","unstructured":"NVIDIA \"NVIDIA's Next Generation CUDA Compute Architecture: Fermi \".  NVIDIA \"NVIDIA's Next Generation CUDA Compute Architecture: Fermi \"."}],"event":{"name":"PACT '12: International Conference on Parallel Architectures and Compilation Techniques","location":"Minneapolis Minnesota USA","acronym":"PACT '12","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"]},"container-title":["Proceedings of the 21st international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370873","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2370816.2370873","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:34:17Z","timestamp":1750224857000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370873"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9,19]]},"references-count":22,"alternative-id":["10.1145\/2370816.2370873","10.1145\/2370816"],"URL":"https:\/\/doi.org\/10.1145\/2370816.2370873","relation":{},"subject":[],"published":{"date-parts":[[2012,9,19]]},"assertion":[{"value":"2012-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}