{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,11]],"date-time":"2025-12-11T20:40:41Z","timestamp":1765485641922,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,9,19]],"date-time":"2012-09-19T00:00:00Z","timestamp":1348012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,9,19]]},"DOI":"10.1145\/2370816.2370888","type":"proceedings-article","created":{"date-parts":[[2012,9,25]],"date-time":"2012-09-25T23:48:43Z","timestamp":1348616923000},"page":"445-446","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Power-efficient computing for compute-intensive GPGPU applications"],"prefix":"10.1145","author":[{"given":"Syed Zohaib","family":"Gilani","sequence":"first","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[{"name":"The University of Wisconsin-Madison, Madison, WI, USA"}]},{"given":"Michael J.","family":"Schulte","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Austin, TX, USA"}]}],"member":"320","published-online":{"date-parts":[[2012,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"GeForce 8800 & NVIDIA CUDA: A new architecture for computing on the GPU. {Online}. www.gpgpu.org  GeForce 8800 & NVIDIA CUDA: A new architecture for computing on the GPU. {Online}. www.gpgpu.org"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.17"},{"key":"e_1_3_2_1_3_1","volume-title":"International technology roadmap for semiconductors","author":"ITRS.","year":"2011","unstructured":"ITRS. ( 2011 ) International technology roadmap for semiconductors . ITRS. (2011) International technology roadmap for semiconductors."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"e_1_3_2_1_5_1","unstructured":"Advanced Micro Devices. Heterogeneous Computing: OpenCL\u2122 and the ATI Radeon\u2122 HD 5870 (\"Evergreen\") architecture. {Online}. http:\/\/developer.amd.com\/gpu_assets\/Heterogeneous_Computing_OpenCL_and_the_ATI_Radeon_HD_5870_Architecture_201003.pdf  Advanced Micro Devices. Heterogeneous Computing: OpenCL\u2122 and the ATI Radeon\u2122 HD 5870 (\"Evergreen\") architecture. {Online}. http:\/\/developer.amd.com\/gpu_assets\/Heterogeneous_Computing_OpenCL_and_the_ATI_Radeon_HD_5870_Architecture_201003.pdf"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1360612.1360617"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_1_8_1","first-page":"235","volume-title":"Demystifying GPU microarchitecture through microbenchmarking,\" in IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)","author":"Wong H.","year":"2010","unstructured":"H. Wong , \" Demystifying GPU microarchitecture through microbenchmarking,\" in IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS) , 2010 , pp. 235 -- 246 . H. Wong et al., \"Demystifying GPU microarchitecture through microbenchmarking,\" in IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), 2010, pp. 235--246."}],"event":{"name":"PACT '12: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"],"location":"Minneapolis Minnesota USA","acronym":"PACT '12"},"container-title":["Proceedings of the 21st international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370888","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2370816.2370888","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:34:17Z","timestamp":1750239257000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2370816.2370888"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9,19]]},"references-count":8,"alternative-id":["10.1145\/2370816.2370888","10.1145\/2370816"],"URL":"https:\/\/doi.org\/10.1145\/2370816.2370888","relation":{},"subject":[],"published":{"date-parts":[[2012,9,19]]},"assertion":[{"value":"2012-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}