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Surv."],"published-print":{"date-parts":[[2012,11]]},"abstract":"<jats:p>Chip multicore processors (CMPs) have emerged as the dominant architecture choice for modern computing platforms and will most likely continue to be dominant well into the foreseeable future. As with any system, CMPs offer a unique set of challenges. Chief among them is the shared resource contention that results because CMP cores are not independent processors but rather share common resources among cores such as the last level cache (LLC). Shared resource contention can lead to severe and unpredictable performance impact on the threads running on the CMP. Conversely, CMPs offer tremendous opportunities for mulithreaded applications, which can take advantage of simultaneous thread execution as well as fast inter thread data sharing. Many solutions have been proposed to deal with the negative aspects of CMPs and take advantage of the positive. This survey focuses on the subset of these solutions that exclusively make use of OS thread-level scheduling to achieve their goals. These solutions are particularly attractive as they require no changes to hardware and minimal or no changes to the OS. The OS scheduler has expanded well beyond its original role of time-multiplexing threads on a single core into a complex and effective resource manager. This article surveys a multitude of new and exciting work that explores the diverse new roles the OS scheduler can successfully take on.<\/jats:p>","DOI":"10.1145\/2379776.2379780","type":"journal-article","created":{"date-parts":[[2012,12,11]],"date-time":"2012-12-11T13:13:42Z","timestamp":1355231622000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":103,"title":["Survey of scheduling techniques for addressing shared resources in multicore processors"],"prefix":"10.1145","volume":"45","author":[{"given":"Sergey","family":"Zhuravlev","sequence":"first","affiliation":[{"name":"Simon Fraser University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Juan Carlos","family":"Saez","sequence":"additional","affiliation":[{"name":"Complutense University of Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sergey","family":"Blagodurov","sequence":"additional","affiliation":[{"name":"Simon Fraser University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alexandra","family":"Fedorova","sequence":"additional","affiliation":[{"name":"Simon Fraser University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Manuel","family":"Prieto","sequence":"additional","affiliation":[{"name":"Complutense University of Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2012,12,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320119"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1504176.1504190"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA'09)","author":"Awasthi M.","unstructured":"Awasthi , M. , Sudan , K. , Balasubramonian , R. , and Carter , J . 2009. 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