{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:37:41Z","timestamp":1761323861133,"version":"3.41.0"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee, Hong Kong","doi-asserted-by":"publisher","award":["123811 and 123210"],"award-info":[{"award-number":["123811 and 123210"]}],"id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,1]]},"abstract":"<jats:p>NAND flash memory has been employed as disk cache in recent years. It has the advantages of high performance, low leakage power, and cost efficiency. However, flash memory's performance is limited by the inability of in-place updates, coarse access granularity, and a limited number of write\/erase times. In this article, we propose a hybrid nonvolatile disk cache architecture for high-performance and energy-efficient systems, where the disk cache is implemented with a small-size phase change memory (PCM) and a large-size NAND flash memory. Compared with current flash memory-based disk cache, it has the following advantages. (1) System performance is improved as requests are carefully directed between PCM and flash memory; (2) the energy consumption of disk cache is substantially reduced with significant reduction of additional operations, such as garbage collections; (3) the efficiency of flash memory is improved with the reduction of write activities on flash memory; and (4) lifetime of NAND flash memory is increased with most of the write operations assigned to PCM, where PCM's lifetime is guaranteed to be longer than the lifetime of flash memory. Simulation results show that the proposed methods can substantially improve the system performance, energy consumption, and lifetime of the hybrid disk cache.<\/jats:p>","DOI":"10.1145\/2390191.2390199","type":"journal-article","created":{"date-parts":[[2013,1,15]],"date-time":"2013-01-15T15:32:11Z","timestamp":1358263931000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Hybrid nonvolatile disk cache for energy-efficient and high-performance systems"],"prefix":"10.1145","volume":"18","author":[{"given":"Liang","family":"Shi","sequence":"first","affiliation":[{"name":"University of Science and Technology of China, and USTC-CityU Joint Advanced Research Centre, Suzhou, P.R.China"}]},{"given":"Jianhua","family":"Li","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, and USTC-CityU Joint Advanced Research Centre, Suzhou, P.R.China"}]},{"given":"Chun","family":"Jason Xue","sequence":"additional","affiliation":[{"name":"City University of Hong Kong, Kowloon, Hong Kong"}]},{"given":"Xuehai","family":"Zhou","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei, China"}]}],"member":"320","published-online":{"date-parts":[[2013,1,16]]},"reference":[{"volume-title":"Proceedings of the USENIX Annual Technical Conference. 57--70","author":"Agrawal N.","key":"e_1_2_1_1_1","unstructured":"Agrawal , N. , Prabhakaran , V. , Wobber , T. , Davis , J. D. , Manasse , M. , and Panigrahy , R . 2008. Design tradeoffs for ssd performance . In Proceedings of the USENIX Annual Technical Conference. 57--70 . Agrawal, N., Prabhakaran, V., Wobber, T., Davis, J. D., Manasse, M., and Panigrahy, R. 2008. Design tradeoffs for ssd performance. In Proceedings of the USENIX Annual Technical Conference. 57--70."},{"key":"e_1_2_1_2_1","unstructured":"Bucy J. S. Schindler J. Schlosser S. W. and Ganger G. R. 2008. The disksim simulation environment version 4.0 reference manual. http:\/\/www.pd\/.cmu.edu\/DiskSim\/.  Bucy J. S. Schindler J. Schlosser S. W. and Ganger G. R. 2008. The disksim simulation environment version 4.0 reference manual. http:\/\/www.pd\/.cmu.edu\/DiskSim\/."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1244002.1244248"},{"volume-title":"Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)","author":"Chang L.-P.","key":"e_1_2_1_4_1","unstructured":"Chang , L.-P. and Kuo , T . -W. 2002. An adaptive striping architecture for flash memory storage systems of embedded systems . In Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02) . 187. Chang, L.-P. and Kuo, T.-W. 2002. An adaptive striping architecture for flash memory storage systems of embedded systems. In Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02). 187."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278533"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.126"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228439"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995902"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Chen Y. Li H. Wang X. Zhu W. Xu W. and Zhang T. 2012b. A 130 nm 1.2 v\/3.3 v 16 kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme. J. Solid-State Circuits 560--573.  Chen Y. Li H. Wang X. Zhu W. Xu W. and Zhang T. 2012b. A 130 nm 1.2 v\/3.3 v 16 kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme. J. Solid-State Circuits 560--573.","DOI":"10.1109\/JSSC.2011.2170778"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/SNAPI.2010.11"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283851"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1534530.1534544"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176774"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.32"},{"volume-title":"Proceedings of the USENIX Conference on File and Storage Technologies (FAST'08)","author":"Kim H.","key":"e_1_2_1_15_1","unstructured":"Kim , H. and Ahn , S . 2008. Bplru: A buffer management scheme for improving random writes in flash storage . In Proceedings of the USENIX Conference on File and Storage Technologies (FAST'08) . 1--14. Kim, H. and Ahn, S. 2008. Bplru: A buffer management scheme for improving random writes in flash storage. In Proceedings of the USENIX Conference on File and Storage Technologies (FAST'08). 1--14."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2011.64"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1982185.1982320"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1275986.1275990"},{"volume-title":"Proceeding of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). 19--28","author":"Li J.","key":"e_1_2_1_21_1","unstructured":"Li , J. , Shi , L. , Xue , C. , Yang , C. , and Xu , Y . 2011. Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache . In Proceeding of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). 19--28 . Li, J., Shi, L., Xue, C., Yang, C., and Xu, Y. 2011. Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache. In Proceeding of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). 19--28."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333738"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.40"},{"volume-title":"Proceedings of the Design, Automation Test in Europe Conference (DATE). 1447--1450","author":"Liu D.","key":"e_1_2_1_24_1","unstructured":"Liu , D. , Wang , T. , Wang , Y. , Qin , Z. , and Shao , Z . 2012. A block-level flash memory management scheme for reducing write activities in pcm-based embedded systems . In Proceedings of the Design, Automation Test in Europe Conference (DATE). 1447--1450 . Liu, D., Wang, T., Wang, Y., Qin, Z., and Shao, Z. 2012. A block-level flash memory management scheme for reducing write activities in pcm-based embedded systems. In Proceedings of the Design, Automation Test in Europe Conference (DATE). 1447--1450."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1367829.1367830"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1519065.1519081"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418973"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176789"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1363686.1364038"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.135"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815982"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_2_1_33_1","unstructured":"Repository U. T. 2007. Oltp application i\/o. http:\/\/traces.cs.umass.edu\/.  Repository U. T. 2007. Oltp application i\/o. http:\/\/traces.cs.umass.edu\/."},{"volume-title":"Proceedings of the USENIX Annual Technical Conference (USENIXATC'10)","author":"Saxena M.","key":"e_1_2_1_34_1","unstructured":"Saxena , M. and Swift , M. M . 2010. Flashvm: Virtual memory management on flash . In Proceedings of the USENIX Annual Technical Conference (USENIXATC'10) . 14--14. Saxena, M. and Swift, M. M. 2010. Flashvm: Virtual memory management on flash. In Proceedings of the USENIX Annual Technical Conference (USENIXATC'10). 14--14."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2038642.2038694"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.22"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785503"},{"key":"e_1_2_1_38_1","unstructured":"Shu F. and Obr N. 2007. Data set management proposal for ata-acs2. http:\/\/www.t13.org\/documents\/UploadedDocuments\/docs2007.  Shu F. and Obr N. 2007. Data set management proposal for ata-acs2. http:\/\/www.t13.org\/documents\/UploadedDocuments\/docs2007."},{"volume-title":"Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). 239--249","author":"Sun G.","key":"e_1_2_1_39_1","unstructured":"Sun , G. , Dong , X. , Xie , Y. , Li , J. , and Chen , Y . 2009. A novel architecture of the 3d stacked mram l2 cache for cmps . In Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). 239--249 . Sun, G., Dong, X., Xie, Y., Li, J., and Chen, Y. 2009. A novel architecture of the 3d stacked mram l2 cache for cmps. In Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). 239--249."},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'10)","author":"Sun G.","key":"e_1_2_1_40_1","unstructured":"Sun , G. , Joo , Y. , Chen , Y. , Niu , D. , Xie , Y. , Chen , Y. , and Li , H . 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement . In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'10) . 1--12. Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., and Li, H. 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'10). 1--12."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039420"},{"volume-title":"Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA'11)","author":"Yang Q.","key":"e_1_2_1_43_1","unstructured":"Yang , Q. and Ren , J . 2011. I-cash: Intelligently coupled array of ssd and hdd . In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA'11) . 278--289. Yang, Q. and Ren, J. 2011. I-cash: Intelligently coupled array of ssd and hdd. In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA'11). 278--289."},{"volume-title":"Proceedings of the USENIX Conference on File and storage Technologies (FAST'12)","author":"Yongseok O.","key":"e_1_2_1_44_1","unstructured":"Yongseok , O. , Jongmoo , C. , Donghee , L. , and Sam , H. N . 2012. Caching less for better performance: Balancing cache size and update cost of flash memory cache in hybrid storage systems . In Proceedings of the USENIX Conference on File and storage Technologies (FAST'12) . 1--14. Yongseok, O., Jongmoo, C., Donghee, L., and Sam, H. N. 2012. Caching less for better performance: Balancing cache size and update cost of flash memory cache in hybrid storage systems. In Proceedings of the USENIX Conference on File and storage Technologies (FAST'12). 1--14."},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2390191.2390199","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2390191.2390199","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:45Z","timestamp":1750235745000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2390191.2390199"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":45,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,1]]}},"alternative-id":["10.1145\/2390191.2390199"],"URL":"https:\/\/doi.org\/10.1145\/2390191.2390199","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2013,1]]},"assertion":[{"value":"2012-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-01-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}