{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:16Z","timestamp":1750306936905,"version":"3.41.0"},"reference-count":8,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,1]]},"abstract":"<jats:p>In order to achieve satisfactory verification for complicated low-power demands in green products, we propose a verification work reduction methodology. It consists of three step, namely virtual, direct actual, and actual model simulations. Virtual low-power simulation inserts low-power cells, such as isolators or level shifters, virtually and simulates logical behavior for design under test (DUT) based on user-defined power mode. Direct actual low-power simulation replaces behavior models without non-logical pins for some of modules with actual models with non-logical pins, which are Vdd and Gnd, and simulates DUT in mixed level. Actual low-power simulation simulates DUT by using actual models with non-logical pins for all cells and hard macros. We introduce techniques which classify the type of the bugs on which we focus at each verification step and prevent the concerned bugs from leaking to the latter verification step as much as possible.<\/jats:p>\n          <jats:p>We applied our methodology to an actual chip and could reduce the total simulation period until tape-out by 38.8% and the total chip development period by 10%, compared with the conventional methodology.<\/jats:p>","DOI":"10.1145\/2390191.2390203","type":"journal-article","created":{"date-parts":[[2013,1,15]],"date-time":"2013-01-15T15:32:11Z","timestamp":1358263931000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Verification work reduction methodology in low-power chip implementation"],"prefix":"10.1145","volume":"18","author":[{"given":"Masanori","family":"Kurimoto","sequence":"first","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takeshi","family":"Yamamoto","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Nakano","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Atsuto","family":"Hanami","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Kondo","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,1,16]]},"reference":[{"volume-title":"Proceedings of the Design and Verification Conference and Exhibition.","author":"Au J.","key":"e_1_2_1_1_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1109\/92.645074"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'08)","author":"Chen S. H.","key":"e_1_2_1_3_1"},{"volume-title":"Proceedings of International Symposium on VLSI Design Automation and Test, (VLSI-DAT'09)","author":"Chen S. H.","key":"e_1_2_1_4_1"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 114--121","author":"Goldberg E. I.","key":"e_1_2_1_5_1"},{"volume-title":"Proceedings of the Design and Verification Conference and Exhibition.","year":"2010","author":"Khan N.","key":"e_1_2_1_6_1"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 55--61","author":"Singh A.","key":"e_1_2_1_7_1"},{"volume-title":"Proceedings of the International SoC Design Conference (ISOCC). 295--300","author":"Yeung P.","key":"e_1_2_1_8_1"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2390191.2390203","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2390191.2390203","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:45Z","timestamp":1750235745000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2390191.2390203"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":8,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,1]]}},"alternative-id":["10.1145\/2390191.2390203"],"URL":"https:\/\/doi.org\/10.1145\/2390191.2390203","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2013,1]]},"assertion":[{"value":"2011-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-01-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}