{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:21:30Z","timestamp":1750306890835,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"FPI","award":["BES-2008-003683"],"award-info":[{"award-number":["BES-2008-003683"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2013,1]]},"abstract":"<jats:p>Processor architectures combining several paradigms of Thread-Level Parallelism (TLP), such as CMP processors in which each core is SMT, are becoming more and more popular as a way to improve performance at a moderate cost. However, the complex interaction between running tasks in hardware shared resources in multi-TLP architectures introduces complexities when accounting CPU time (or CPU utilization) to tasks. The CPU utilization accounted to a task depends on both the time it runs in the processor and the amount of processor hardware resources it receives. Deploying systems with accurate CPU accounting mechanisms is necessary to increase fairness. Moreover, it will allow users to be fairly charged on a shared data center, facilitating server consolidation in future systems.<\/jats:p>\n          <jats:p>In this article we analyze the accuracy and hardware cost of previous CPU accounting mechanisms for pure-CMP and pure-SMT processors and we show that they are not adequate for CMP+SMT processors. Consequently, we propose a new accounting mechanism for CMP+SMT processors which: (1) increases the accuracy of accounted CPU utilization; (2) provides much more stable results over a wide range of processor setups; and (3) does not require tracking all hardware shared resources, significantly reducing its implementation cost. In particular, previous proposals lead to inaccuracies between 21% and 79% when measuring CPU utilization in an 8-core 2-way SMT processor, while our proposal reduces this inaccuracy to less than 5.0%.<\/jats:p>","DOI":"10.1145\/2400682.2400709","type":"journal-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:28:56Z","timestamp":1358868536000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Fair CPU time accounting in CMP+SMT processors"],"prefix":"10.1145","volume":"9","author":[{"given":"Carlos","family":"Luque","sequence":"first","affiliation":[{"name":"Universistat Polit\u00e8cnica de Catalunya, and Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miquel","family":"Moreto","sequence":"additional","affiliation":[{"name":"International Computer Science Institute, Universistat Polit\u00e8cnica de Catalunya, and Barcelona Supercomputing Center, Berkeley, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, and Spanish National Research Council (IIIA-CSIC), Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"Universistat Polit\u00e8cnica de Catalunya, and Barcelona Supercomputing Center), Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,1,20]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Acosta C. Cazorla F. J. Ramirez A. and Valero M. 2009. The MPsim simulation tool. http:\/\/capinfo.e.ac.upc.edu\/PDFs\/dir21\/file003472.pdf.  Acosta C. Cazorla F. J. Ramirez A. and Valero M. 2009. The MPsim simulation tool. http:\/\/capinfo.e.ac.upc.edu\/PDFs\/dir21\/file003472.pdf."},{"volume-title":"MIT","author":"Agarwal A.","key":"e_1_2_1_2_1","unstructured":"Agarwal , A. , Lim , B. -H. , Kranz , D. , Kubiatowicz , J. 1991. A processor architecture for multiprocessing. Tech. rep. MIT\/LCS\/TM-450 , MIT , http:\/\/www.dtic.mil\/dtic\/tr\/fulltext\/u2\/a237476.pdf. Agarwal, A., Lim, B. -H., Kranz, D.,Kubiatowicz, J. 1991. A processor architecture for multiprocessing. Tech. rep. MIT\/LCS\/TM-450, MIT, http:\/\/www.dtic.mil\/dtic\/tr\/fulltext\/u2\/a237476.pdf."},{"key":"e_1_2_1_3_1","volume-title":"Cipher Systems: The Protection of Communications","author":"Beker H.","year":"1982","unstructured":"Beker , H. and Piper , F . 1982 . Cipher Systems: The Protection of Communications . Wiley-Interscience . Beker, H. and Piper, F. 1982. Cipher Systems: The Protection of Communications. Wiley-Interscience."},{"key":"e_1_2_1_4_1","unstructured":"Broyles M. Francois C. Geissler A. Hollinger M. Rosedahl T. etal 2011. IBM energyscale for POWER7 processor-based systems. http:\/\/www.ibm.com\/systems\/power\/hardware\/whitepapers\/energyscale7.html.  Broyles M. Francois C. Geissler A. Hollinger M. Rosedahl T. et al. 2011. IBM energyscale for POWER7 processor-based systems. http:\/\/www.ibm.com\/systems\/power\/hardware\/whitepapers\/energyscale7.html."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086320"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594292"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736058"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168880"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508260"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299108"},{"key":"e_1_2_1_11_1","first-page":"5","volume-title":"Advanced POWER Virtualization on IBM eServer","author":"Gibbs B.","unstructured":"Gibbs , B. , Pulles , M. , Advanced POWER Virtualization on IBM eServer p 5 Servers : Architecture and Performance Considerations. IBM Redbook . Gibbs, B., Pulles, M., et al. 2006. Advanced POWER Virtualization on IBM eServer p5 Servers: Architecture and Performance Considerations. IBM Redbook."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.6"},{"volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA'88)","author":"Halstead R.","key":"e_1_2_1_13_1","unstructured":"Halstead , R. and Fujita , T . 1988. MASA: A multithreaded processor architecture for parallel symbolic computing . In Proceedings of the International Symposium on Computer Architecture (ISCA'88) . Halstead, R. and Fujita, T. 1988. MASA: A multithreaded processor architecture for parallel symbolic computing. In Proceedings of the International Symposium on Computer Architecture (ISCA'88)."},{"key":"e_1_2_1_14_1","unstructured":"ITRS. 2011. International technology roadmap for semiconductors. http:\/\/www.itrs.net.  ITRS. 2011. International technology roadmap for semiconductors. http:\/\/www.itrs.net."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.48"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.33"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.152"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.43"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/248209.237140"},{"key":"e_1_2_1_24_1","unstructured":"Oracle. 2012. White paper. Oracle's sparc t4-1 sparc t4-2 sparc t4-4 and sparc t4-1b server architecture. http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/o1.  Oracle. 2012. White paper. Oracle's sparc t4-1 sparc t4-2 sparc t4-4 and sparc t4-1b server architecture. http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/o1."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'03)","author":"Raasch S. E.","key":"e_1_2_1_26_1","unstructured":"Raasch , S. E. and Reinhardt , S. K . 2003. The impact of resource partitioning on smt processors . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'03) . Raasch, S. E. and Reinhardt, S. K. 2003. The impact of resource partitioning on smt processors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'03)."},{"volume-title":"Proceedings of the Symposium on High Performance Chips (HotChips'11)","author":"Rotem E.","key":"e_1_2_1_27_1","unstructured":"Rotem , E. , Naveh , A. , Rajwan , D. , Ananthakrishnan , A. , and Weissmann , E . 2011. Power management architecture of the 2nd generation intel core microarchitecture, formerly codenamed sandy bridge . In Proceedings of the Symposium on High Performance Chips (HotChips'11) . Rotem, E., Naveh, A., Rajwan, D., Ananthakrishnan, A., and Weissmann, E. 2011. Power management architecture of the 2nd generation intel core microarchitecture, formerly codenamed sandy bridge. In Proceedings of the Symposium on High Performance Chips (HotChips'11)."},{"key":"e_1_2_1_28_1","unstructured":"Serrano M. J. Wood R. and Nemirovsky M. 1993. A study on multistreamed superscalar processors. Tech. rep. 93-05 University of California Santa Barbara.  Serrano M. J. Wood R. and Nemirovsky M. 1993. A study on multistreamed superscalar processors. Tech. rep. 93-05 University of California Santa Barbara."},{"volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'01)","author":"Sherwood T.","key":"e_1_2_1_29_1","unstructured":"Sherwood , T. , Perelman , E. , and Calder , B . 2001. Basic block distribution analysis to find periodic behavior and simulation points in applications . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'01) . Sherwood, T., Perelman, E., and Calder, B. 2001. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'01)."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2127330"},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the 4th Symposium on Real Time Signal Processing.","author":"Smith B.","year":"1981","unstructured":"Smith , B. 1981 . Architecture and applications of the hep multiprocessor computer system . In Proceedings of the 4th Symposium on Real Time Signal Processing. Smith, B. 1981. Architecture and applications of the hep multiprocessor computer system. In Proceedings of the 4th Symposium on Real Time Signal Processing."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511343"},{"volume-title":"Proceedings of the 45th International Solid-State Circuits Conference.","author":"Storino S.","key":"e_1_2_1_34_1","unstructured":"Storino , S. , Aipperspach , A. , Borkenhagen , J. , Eickemeyer , R. , Kunkel , S. , Levenstein , S. , and Uhlmann , G . 1988. A commercial multithreaded risc processor . In Proceedings of the 45th International Solid-State Circuits Conference. Storino, S., Aipperspach, A., Borkenhagen, J., Eickemeyer, R., Kunkel, S., Levenstein, S., and Uhlmann, G. 1988. A commercial multithreaded risc processor. In Proceedings of the 45th International Solid-State Circuits Conference."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224449"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086328"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2400682.2400709","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2400682.2400709","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:52Z","timestamp":1750234732000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2400682.2400709"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":36,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,1]]}},"alternative-id":["10.1145\/2400682.2400709"],"URL":"https:\/\/doi.org\/10.1145\/2400682.2400709","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2013,1]]},"assertion":[{"value":"2012-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-01-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}