{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:29:22Z","timestamp":1750307362023,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1145\/2401716.2401719","type":"proceedings-article","created":{"date-parts":[[2012,11,27]],"date-time":"2012-11-27T14:28:59Z","timestamp":1354026539000},"page":"5-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Network on metachip architectures"],"prefix":"10.1145","author":[{"given":"Ismo","family":"H\u00e4nninen","sequence":"first","affiliation":[{"name":"Univ. of Notre Dame, Notre Dame, IN and Tampere University of Technology, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Buckhanan","sequence":"additional","affiliation":[{"name":"Univ. of Notre Dame, Notre Dame, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Niemier","sequence":"additional","affiliation":[{"name":"Univ. of Notre Dame, Notre Dame, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gary H.","family":"Bernstein","sequence":"additional","affiliation":[{"name":"Univ. of Notre Dame, Notre Dame, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,12]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"ITRS report. {Online}. Available: http:\/\/www.itrs.net\/Links\/2011ITRS\/Home2011.htm","author":"Semiconductors International Technology","year":"2011","unstructured":"International Technology Roadmap for Semiconductors . ( 2011 ) ITRS report. {Online}. Available: http:\/\/www.itrs.net\/Links\/2011ITRS\/Home2011.htm International Technology Roadmap for Semiconductors. (2011) ITRS report. {Online}. Available: http:\/\/www.itrs.net\/Links\/2011ITRS\/Home2011.htm"},{"key":"e_1_3_2_1_2_1","unstructured":"Quilt Packaging\u00ae is a registered trademark of Indiana Integrated Circuits LLC  Quilt Packaging\u00ae is a registered trademark of Indiana Integrated Circuits LLC"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2007.901643"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.4071\/1551-4897-4.1.1"},{"key":"e_1_3_2_1_5_1","first-page":"309","volume-title":"Quilt Packaging: A Coplanar Chip-to-Chip Interconnect Offering Ultra-Wide Bandwidth,\" in Proc. of 2010 International Conference on Compound Semiconductor Manufacturing Technology (CS Mantech)","author":"Kopp D.","year":"2010","unstructured":"D. Kopp , M. A. Khan , S. Garvey , K. Anderson , J. Kulick , P. Fay , A. M. Kriman , and G. H. Bernstein , \" Quilt Packaging: A Coplanar Chip-to-Chip Interconnect Offering Ultra-Wide Bandwidth,\" in Proc. of 2010 International Conference on Compound Semiconductor Manufacturing Technology (CS Mantech) , p. 309 ( 2010 ). D. Kopp, M. A. Khan, S. Garvey, K. Anderson, J. Kulick, P. Fay, A. M. Kriman, and G. H. Bernstein, \"Quilt Packaging: A Coplanar Chip-to-Chip Interconnect Offering Ultra-Wide Bandwidth,\" in Proc. of 2010 International Conference on Compound Semiconductor Manufacturing Technology (CS Mantech), p. 309 (2010)."},{"key":"e_1_3_2_1_6_1","unstructured":"M. D. Marino and K. Skadron. \"Reducing Power and Area by Interconnecting Memory Controllers to Memory Ranks with RF Coplanar Waveguides on the Same Package.\" In Proceedings of the 3rd Workshop on Energy-Efficient Design (WEED) in conjunction with ISCA June 2011  M. D. Marino and K. Skadron. \"Reducing Power and Area by Interconnecting Memory Controllers to Memory Ranks with RF Coplanar Waveguides on the Same Package.\" In Proceedings of the 3rd Workshop on Energy-Efficient Design (WEED) in conjunction with ISCA June 2011"},{"key":"e_1_3_2_1_7_1","first-page":"166","volume-title":"Micro\/Nano Symposium (UGIM)","author":"Khan M. A.","year":"2010","unstructured":"M. A. Khan , A. M. Kriman , and G. H. Bernstein , \" Thermal Modeling of Quilt Packaging Interconnects,\" Proc . Micro\/Nano Symposium (UGIM) , pp. 166 -- 168 ( 2010 ). M. A. Khan, A. M. Kriman, and G. H. Bernstein, \"Thermal Modeling of Quilt Packaging Interconnects,\" Proc. Micro\/Nano Symposium (UGIM), pp. 166--168 (2010)."},{"key":"e_1_3_2_1_8_1","unstructured":"Stephen W. Director W. Maly \"Statistical approach to VLSI\". North-Holland (1994).  Stephen W. Director W. Maly \"Statistical approach to VLSI\". North-Holland (1994)."},{"key":"e_1_3_2_1_9_1","unstructured":"Quanling Zheng unpublished.  Quanling Zheng unpublished."},{"key":"e_1_3_2_1_10_1","volume-title":"Performance Evaluation Corporation Suite SPEC CPU2006","author":"Standard","year":"2006","unstructured":"Standard Performance Evaluation Corporation Suite SPEC CPU2006 . {Online}. Available : http:\/\/www.spec.org\/cpu 2006 \/ Standard Performance Evaluation Corporation Suite SPEC CPU2006. {Online}. Available: http:\/\/www.spec.org\/cpu2006\/"},{"key":"e_1_3_2_1_11_1","volume-title":"Wind River Systems\/Intel","author":"Full-System Simulator Simics","year":"2010","unstructured":"Simics Full-System Simulator . Wind River Systems\/Intel ( 2010 ). {Online}. Available: http:\/\/www.windriver.com\/products\/simics\/ Simics Full-System Simulator. Wind River Systems\/Intel (2010). {Online}. Available: http:\/\/www.windriver.com\/products\/simics\/"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.14"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2037368"},{"key":"e_1_3_2_1_14_1","volume-title":"JEDEC Standard. {Online}. Available: http:\/\/www.jedec.org\/standards-documents\/docs\/jesd-8-15a","author":"JEDEC","year":"2003","unstructured":"JEDEC SSTL_18. ( 2003 ) JEDEC Standard. {Online}. Available: http:\/\/www.jedec.org\/standards-documents\/docs\/jesd-8-15a JEDEC SSTL_18. (2003) JEDEC Standard. {Online}. Available: http:\/\/www.jedec.org\/standards-documents\/docs\/jesd-8-15a"},{"key":"e_1_3_2_1_15_1","volume-title":"ISO Standard","author":"Open Systems","year":"1994","unstructured":"Open Systems Interconnection (OSI) model (ISO\/IEC 7498-1). ( 1994 ) ISO Standard . Open Systems Interconnection (OSI) model (ISO\/IEC 7498-1). (1994) ISO Standard."}],"event":{"name":"NoCArc '12: Fifth International Workshop on Network on Chip Architectures","acronym":"NoCArc '12","location":"Vancouver British Columbia Canada"},"container-title":["Proceedings of the Fifth International Workshop on Network on Chip Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2401716.2401719","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2401716.2401719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:32Z","timestamp":1750245752000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2401716.2401719"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":15,"alternative-id":["10.1145\/2401716.2401719","10.1145\/2401716"],"URL":"https:\/\/doi.org\/10.1145\/2401716.2401719","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]},"assertion":[{"value":"2012-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}