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Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,2]]},"abstract":"<jats:p>Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automatic synthesis algorithm for the architecture. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks.<\/jats:p>","DOI":"10.1145\/2422094.2422099","type":"journal-article","created":{"date-parts":[[2013,2,22]],"date-time":"2013-02-22T19:25:04Z","timestamp":1361561104000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays"],"prefix":"10.1145","volume":"9","author":[{"given":"Yung-Chih","family":"Chen","sequence":"first","affiliation":[{"name":"Chung Yuan Christian University"}]},{"given":"Soumya","family":"Eachempati","sequence":"additional","affiliation":[{"name":"Intel Corporation"}]},{"given":"Chun-Yao","family":"Wang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University"}]},{"given":"Suman","family":"Datta","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]}],"member":"320","published-online":{"date-parts":[[2013,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024920"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2008.4585793"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1386-9477(01)00193-X"},{"volume-title":"Proceedings of the International Symposium on Semiconductor Device Research. 622--625","author":"Kasai S.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","unstructured":"Keating M. Flynn D. Aitken R. Gibbons A. and Shi K. 2007. Low Power Methodology Manual: For System-on-Chip Design. Springer.   Keating M. Flynn D. Aitken R. Gibbons A. and Shi K. 2007. Low Power Methodology Manual: For System-on-Chip Design . Springer."},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Keckler S. W. Olukotun K. and Hofstee H. P. 2009. Multicore Processors and Systems. Springer.   Keckler S. W. Olukotun K. and Hofstee H. P. 2009. Multicore Processors and Systems . Springer.","DOI":"10.1007\/978-1-4419-0263-4"},{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting.","author":"Liu L.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Piguet C. 2006. Low-Power CMOS Circuits: Technology Logic Design and CAD Tools. CRC Press.  Piguet C. 2006. Low-Power CMOS Circuits: Technology Logic Design and CAD Tools . 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