{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:21:21Z","timestamp":1750306881604,"version":"3.41.0"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2013,2,1]],"date-time":"2013-02-01T00:00:00Z","timestamp":1359676800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006445","name":"Center for Hierarchical Manufacturing, National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006445","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Focus Center Research Program"},{"name":"Center on Functionally Engineering Nano Architectonics"},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCR:0105516, NER:0508382, CCR:051066"],"award-info":[{"award-number":["CCR:0105516, NER:0508382, CCR:051066"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,2]]},"abstract":"<jats:p>\n            Nano\/molecular technologies have emerged as the potential fabrics for building future integrated systems. However, due to the imperfect fabrication process, these extremely scaled devices are vulnerable to a large number of defects and transient faults. Memory systems, which are the primary application targeted by these technologies, are particularly exposed to this problem due to the ultra-high integration density and elevated error sensitivity. In this article, we propose a defect-tolerant technique, referred to as\n            <jats:italic>hybrid redundancy allocation<\/jats:italic>\n            , for the design of molecular crossbar memory systems. By using soft redundancy (runtime exploitation of memory spatial\/temporal locality) in combination with hardware redundancy (spare memory cells), the proposed technique can achieve better error management at a low cost as compared with conventional techniques. Simulation results demonstrate the significant improvement in defect tolerance, efficiency, and scalability of the proposed technique.\n          <\/jats:p>","DOI":"10.1145\/2422094.2422101","type":"journal-article","created":{"date-parts":[[2013,2,22]],"date-time":"2013-02-22T19:25:04Z","timestamp":1361561104000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory"],"prefix":"10.1145","volume":"9","author":[{"given":"Shuo","family":"Wang","sequence":"first","affiliation":[{"name":"University of Connecticut"}]},{"given":"Jianwei","family":"Dai","sequence":"additional","affiliation":[{"name":"University of Connecticut"}]},{"given":"Lei","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Connecticut"}]}],"member":"320","published-online":{"date-parts":[[2013,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.926572"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/14\/4\/311"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1559439"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1777401.1777402"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968299"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.816658"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2004.837849"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002303"},{"key":"e_1_2_1_10_1","unstructured":"Edler J. and Hill M. D. Dinero IV trace-driven uniprocessor cache simulator http:\/\/www.cs.wisc.edu\/~markhill\/DineroIV\/.  Edler J. and Hill M. D. Dinero IV trace-driven uniprocessor cache simulator http:\/\/www.cs.wisc.edu\/~markhill\/DineroIV\/."},{"volume-title":"Proceedings of the International Conference on Nano-Networks. 1--5.","author":"Gojman B.","key":"e_1_2_1_11_1","unstructured":"Gojman , B. , Rubin , R. , Pilotto , C. , DeHon , A. , and Tanamoto , T . 2006. 3D nanowire-based programmable logic . In Proceedings of the International Conference on Nano-Networks. 1--5. Gojman, B., Rubin, R., Pilotto, C., DeHon, A., and Tanamoto, T. 2006. 3D nanowire-based programmable logic. In Proceedings of the International Conference on Nano-Networks. 1--5."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2002.807393"},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","unstructured":"Huang Y. Duan X. Cui Y. Lauhon L. J. Kim K-Y. and Lieber C. M. 2011. Logic gates and computation from assembled nanowire building blocks. Science 294 5545 1313--1317.  Huang Y. Duan X. Cui Y. Lauhon L. J. Kim K-Y. and Lieber C. M. 2011. Logic gates and computation from assembled nanowire building blocks. Science 294 5545 1313--1317.","DOI":"10.1126\/science.1066192"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.877431"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.285750"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3164-2"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2004.824011"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/4\/1\/004"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2007.4400865"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1324177.1324180"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0136"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513944"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.663544"},{"key":"e_1_2_1_24_1","doi-asserted-by":"crossref","unstructured":"McCreery R. L. and Bergren A. J. 2009. Progress with molecular electronic junctions: meeting experimental challenges in design and fabrication. Adv. Mater. 21 43 4303C4322.  McCreery R. L. and Bergren A. J. 2009. Progress with molecular electronic junctions: meeting experimental challenges in design and fabrication. Adv. Mater. 21 43 4303C4322.","DOI":"10.1002\/adma.200802850"},{"volume-title":"Proceedings of the IEEE Annual Workshop on Workload Characterization. 99--107","author":"Milenkovic A.","key":"e_1_2_1_25_1","unstructured":"Milenkovic , A. and Milenkovic , M . 2003. Exploiting streams in instruction and data address trace compression . In Proceedings of the IEEE Annual Workshop on Workload Characterization. 99--107 . Milenkovic, A. and Milenkovic, M. 2003. Exploiting streams in instruction and data address trace compression. In Proceedings of the IEEE Annual Workshop on Workload Characterization. 99--107."},{"volume-title":"Proceedings of the International Test Conference. 1201--1211","author":"Mishra M.","key":"e_1_2_1_26_1","unstructured":"Mishra , M. and Goldstein , S. C . 2003. Defect tolerance at the end of the roadmap . In Proceedings of the International Test Conference. 1201--1211 . Mishra, M. and Goldstein, S. C. 2003. Defect tolerance at the end of the roadmap. In Proceedings of the International Test Conference. 1201--1211."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302493.1302760"},{"key":"e_1_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Naeimi H. and DeHon A. 2008. Fault-tolerant sub-lithographic design with rollback recovery. Nanotechnology 1--17.  Naeimi H. and DeHon A. 2008. Fault-tolerant sub-lithographic design with rollback recovery. Nanotechnology 1--17.","DOI":"10.1088\/0957-4484\/19\/11\/115708"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.118653"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. 77--82","author":"Paul S.","key":"e_1_2_1_30_1","unstructured":"Paul , S. and Bhunia , S . 2008. MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices . In Proceedings of the Asia and South Pacific Design Automation Conference. 77--82 . Paul, S. and Bhunia, S. 2008. MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. In Proceedings of the Asia and South Pacific Design Automation Conference. 77--82."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2009875"},{"volume-title":"Introduction to Error-Correcting Codes","author":"Purser M.","key":"e_1_2_1_32_1","unstructured":"Purser , M. 1994. Introduction to Error-Correcting Codes . Artech House Publishers . Purser, M. 1994. Introduction to Error-Correcting Codes. Artech House Publishers."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/18\/3\/035204"},{"volume-title":"CPU2000","author":"SPEC","key":"e_1_2_1_34_1","unstructured":"SPEC CPU2000 . http:\/\/www.spec.org\/cpu\/. SPEC CPU2000. http:\/\/www.spec.org\/cpu\/."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2007.893572"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/1129601.1129697"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629091.1629094"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.305"},{"volume-title":"Probabilistic logics and the synthesis of reliable organisms from unreliable components","author":"Von Neumann J.","key":"e_1_2_1_39_1","unstructured":"Von Neumann , J. 1956. Probabilistic logics and the synthesis of reliable organisms from unreliable components . In Automata Studies, C. Shannon and J. McCarthy Eds., Princeton University Press. Von Neumann, J. 1956. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In Automata Studies, C. Shannon and J. McCarthy Eds., Princeton University Press."},{"volume-title":"Proceedings of the IEEE International Conference on Nanotechnology. 707--710","author":"Wang S.","key":"e_1_2_1_40_1","unstructured":"Wang , S. and Wang , L . 2008. A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy . In Proceedings of the IEEE International Conference on Nanotechnology. 707--710 . Wang, S. and Wang, L. 2008. A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy. In Proceedings of the IEEE International Conference on Nanotechnology. 707--710."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001743"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977161"},{"volume-title":"Proceedings of Nanotech\u201908","author":"Wang T.","key":"e_1_2_1_43_1","unstructured":"Wang , T. , Ben-Naser , M. , Guo , Y. , and Moritz , C. A . 2005. Wire-streaming processor on 2-D nanowire fabrics . In Proceedings of Nanotech\u201908 . Nano Science and Technology Institute. Wang, T., Ben-Naser, M., Guo, Y., and Moritz, C. A. 2005. Wire-streaming processor on 2-D nanowire fabrics. In Proceedings of Nanotech\u201908. Nano Science and Technology Institute."},{"key":"e_1_2_1_44_1","unstructured":"Williams S. and Kuekes P. 2001 Demultiplexer for a molecular wire crossbar network. U.S. Patent 6 256 767.  Williams S. and Kuekes P. 2001 Demultiplexer for a molecular wire crossbar network. U.S. Patent 6 256 767."},{"volume-title":"Proceedings of the IEEE Conference on Nanotechnology. 1100--1103","author":"Wu J.","key":"e_1_2_1_45_1","unstructured":"Wu , J. and Choi , M . 2010 Memristor lookup table (MLUT)-based asynchronous nanowire crossbar architecture . In Proceedings of the IEEE Conference on Nanotechnology. 1100--1103 . Wu, J. and Choi, M. 2010 Memristor lookup table (MLUT)-based asynchronous nanowire crossbar architecture. In Proceedings of the IEEE Conference on Nanotechnology. 1100--1103."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3176-y"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.37"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2422094.2422101","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2422094.2422101","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:35Z","timestamp":1750234715000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2422094.2422101"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":47,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,2]]}},"alternative-id":["10.1145\/2422094.2422101"],"URL":"https:\/\/doi.org\/10.1145\/2422094.2422101","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2013,2]]},"assertion":[{"value":"2011-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-02-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}