{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T21:18:56Z","timestamp":1772572736154,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,11,5]],"date-time":"2012-11-05T00:00:00Z","timestamp":1352073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS-1116684CNS-1149654"],"award-info":[{"award-number":["CNS-1116684CNS-1149654"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,11,5]]},"DOI":"10.1145\/2429384.2429401","type":"proceedings-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:29:29Z","timestamp":1358868569000},"page":"88-94","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":58,"title":["Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches"],"prefix":"10.1145","author":[{"given":"Xiuyuan","family":"Bi","sequence":"first","affiliation":[{"name":"Polytechnic Institute of New York University, Brooklyn, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenyu","family":"Sun","sequence":"additional","affiliation":[{"name":"Polytechnic Institute of New York University, Brooklyn, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hai","family":"Li","sequence":"additional","affiliation":[{"name":"Polytechnic Institute of New York University, Brooklyn, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenqing","family":"Wu","sequence":"additional","affiliation":[{"name":"Qualcomm Incorporated, San Diego, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"The International Technology Roadmap for Semiconductors \" http:\/\/www.itrs.net 2010.  \"The International Technology Roadmap for Semiconductors \" http:\/\/www.itrs.net 2010."},{"key":"e_1_3_2_1_2_1","first-page":"73","volume-title":"Processor caches built using multi-level spin-transfer torque RAM cells,\" in Int'l Symposium on Low Power Electronics and Design (ISLPED)","author":"Chen Y.","year":"2011","unstructured":"Y. Chen , \" Processor caches built using multi-level spin-transfer torque RAM cells,\" in Int'l Symposium on Low Power Electronics and Design (ISLPED) , 2011 , pp. 73 -- 78 . Y. Chen et al., \"Processor caches built using multi-level spin-transfer torque RAM cells,\" in Int'l Symposium on Low Power Electronics and Design (ISLPED), 2011, pp. 73--78."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2035509"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973030"},{"key":"e_1_3_2_1_7_1","first-page":"459","article-title":"A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram","author":"Hosomi M.","year":"2005","unstructured":"M. Hosomi , \" A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram ,\" in IEDM , 2005 , pp. 459 -- 462 . M. Hosomi et al., \"A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram,\" in IEDM, 2005, pp. 459--462.","journal-title":"IEDM"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.909751"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"e_1_3_2_1_10_1","first-page":"471","volume-title":"Stt-ram cell design optimization for persistent and non-persistent error rate reduction: A statistical design view,\" in International Conference on Computer Aided Design (ICCAD)","author":"Zhang Y.","year":"2011","unstructured":"Y. Zhang , \" Stt-ram cell design optimization for persistent and non-persistent error rate reduction: A statistical design view,\" in International Conference on Computer Aided Design (ICCAD) , 2011 , pp. 471 -- 477 . Y. Zhang et al., \"Stt-ram cell design optimization for persistent and non-persistent error rate reduction: A statistical design view,\" in International Conference on Computer Aided Design (ICCAD), 2011, pp. 471--477."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2837800"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.71.024411"},{"key":"e_1_3_2_1_13_1","first-page":"1301","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Bi X.","year":"2012","unstructured":"X. Bi memristor based temperature sensor design with cmos current reference,\" in Design , Automation Test in Europe Conference Exhibition (DATE) , 2012 , pp. 1301 -- 1306 . X. Bi et al., \"Spintronic memristor based temperature sensor design with cmos current reference,\" in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 1301--1306."},{"key":"e_1_3_2_1_14_1","first-page":"1","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Xu C.","year":"2011","unstructured":"C. Xu implications of memristor-based rram cross-point structures,\" in Design , Automation Test in Europe Conference Exhibition (DATE) , 2011 , pp. 1 -- 6 . C. Xu et al., \"Design implications of memristor-based rram cross-point structures,\" in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1--6."},{"key":"e_1_3_2_1_15_1","volume-title":"dissertation","author":"Bienia C.","year":"2011","unstructured":"C. Bienia , \"Benchmarking modern multiprocessors,\" Ph. D. dissertation , Princeton University , January 2011 . C. Bienia, \"Benchmarking modern multiprocessors,\" Ph.D. dissertation, Princeton University, January 2011."},{"key":"e_1_3_2_1_16_1","unstructured":"\"Wind River Simics \" http:\/\/www.windriver.com\/products\/simics\/.  \"Wind River Simics \" http:\/\/www.windriver.com\/products\/simics\/."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391610"},{"key":"e_1_3_2_1_18_1","first-page":"239","volume-title":"A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs,\" in Int'l Symposium on High Performance Computer Architecture (HPCA)","author":"Sun G.","year":"2009","unstructured":"G. Sun , \" A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs,\" in Int'l Symposium on High Performance Computer Architecture (HPCA) , 2009 , pp. 239 -- 249 . G. Sun et al., \"A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs,\" in Int'l Symposium on High Performance Computer Architecture (HPCA), 2009, pp. 239--249."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"}],"event":{"name":"ICCAD '12: The International Conference on Computer-Aided Design","location":"San Jose California","acronym":"ICCAD '12","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429401","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2429384.2429401","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:25Z","timestamp":1750235725000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429401"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11,5]]},"references-count":19,"alternative-id":["10.1145\/2429384.2429401","10.1145\/2429384"],"URL":"https:\/\/doi.org\/10.1145\/2429384.2429401","relation":{},"subject":[],"published":{"date-parts":[[2012,11,5]]},"assertion":[{"value":"2012-11-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}