{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:42:00Z","timestamp":1761561720256,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,11,5]],"date-time":"2012-11-05T00:00:00Z","timestamp":1352073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,11,5]]},"DOI":"10.1145\/2429384.2429409","type":"proceedings-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:29:29Z","timestamp":1358868569000},"page":"130-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Maze routing algorithms with exact matching constraints for analog and mixed signal designs"],"prefix":"10.1145","author":[{"given":"Muhammet Mustafa","family":"Ozdal","sequence":"first","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}]},{"given":"Renato Fernandes","family":"Hentschke","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}]}],"member":"320","published-online":{"date-parts":[[2012,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"M. Bai and etal \"A 65nm logic technology featuring 35nm gate length enhanced channel strain 8 cu interconnect layers low-k ILD and 0.57um2 SRAM cell \" in Proc. of IEDM 2004.  M. Bai and et al. \"A 65nm logic technology featuring 35nm gate length enhanced channel strain 8 cu interconnect layers low-k ILD and 0.57 um 2 SRAM cell \" in Proc. of IEDM 2004."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.75012"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Q. Gao H. Yao Q. Zhou and Y. Cai \"A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits \" in Proc. of ISQED 2011.  Q. Gao H. Yao Q. Zhou and Y. Cai \"A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits \" in Proc. of ISQED 2011.","DOI":"10.1109\/ISQED.2011.5770700"},{"key":"e_1_3_2_1_4_1","first-page":"175","article-title":"Analog routing for manufacturability","author":"Lampaert K.","year":"1996","journal-title":"Proc of"},{"key":"e_1_3_2_1_5_1","first-page":"1","article-title":"A matching-based placement and routing system for analog design","author":"Lin P.-H.","year":"2007","journal-title":"Proc. of VLSI-DAT"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"S. Mitra S. K. Nag R. A. Rutenbar and L. R. Carley \"System-level routing of mixed-signal ASICs in WREN \" in Proc. of ICCAD 1992.   S. Mitra S. K. Nag R. A. Rutenbar and L. R. Carley \"System-level routing of mixed-signal ASICs in WREN \" in Proc. of ICCAD 1992.","DOI":"10.1109\/ICCAD.1992.279339"},{"key":"e_1_3_2_1_7_1","unstructured":"G.-J. Nam \"ISPD 2007 Global Routing Contest \" 2007.  G.-J. Nam \"ISPD 2007 Global Routing Contest \" 2007."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687442"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853685"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882584"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124726"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"T. Yan and M. D. F. Wong \"BSG-Route: A length-matching router for general topology \" in Proc. of ICCAD 2008.   T. Yan and M. D. F. Wong \"BSG-Route: A length-matching router for general topology \" in Proc. of ICCAD 2008.","DOI":"10.1109\/ICCAD.2008.4681621"}],"event":{"name":"ICCAD '12: The International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"],"location":"San Jose California","acronym":"ICCAD '12"},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429409","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2429384.2429409","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:25Z","timestamp":1750235725000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429409"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11,5]]},"references-count":12,"alternative-id":["10.1145\/2429384.2429409","10.1145\/2429384"],"URL":"https:\/\/doi.org\/10.1145\/2429384.2429409","relation":{},"subject":[],"published":{"date-parts":[[2012,11,5]]},"assertion":[{"value":"2012-11-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}