{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:04:14Z","timestamp":1761581054498,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":74,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,11,5]],"date-time":"2012-11-05T00:00:00Z","timestamp":1352073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-1017778CCF-1162267"],"award-info":[{"award-number":["CCF-1017778CCF-1162267"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2012-TJ-2234"],"award-info":[{"award-number":["2012-TJ-2234"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,11,5]]},"DOI":"10.1145\/2429384.2429431","type":"proceedings-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:29:29Z","timestamp":1358868569000},"page":"243-246","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Circuit reliability"],"prefix":"10.1145","author":[{"given":"Jianxin","family":"Fang","sequence":"first","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saket","family":"Gupta","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay V.","family":"Kumar","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sravan K.","family":"Marella","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"Mishra","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pingqiang","family":"Zhou","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota, Minneapolis, MN"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.53"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.03.019"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"M. A. Alam \"A critical examination of the mechanics of dynamic NBTI for pMOSFETs \" IEEE International Electronic Devices Meeting pp. 14.4.1--14.4.4 2003. M. A. Alam \"A critical examination of the mechanics of dynamic NBTI for pMOSFETs \" IEEE International Electronic Devices Meeting pp. 14.4.1--14.4.4 2003.","DOI":"10.1109\/IEDM.2003.1269295"},{"key":"e_1_3_2_1_4_1","first-page":"14.5.1","volume-title":"NBTI impact on transistor and circuit: Models, mechanisms and scaling effects,\" IEEE International Electronic Devices Meeting","author":"Krishnan A. T.","year":"2003","unstructured":"A. T. Krishnan , V. Reddy , S. Chakravarthi , J. Rodriguez , S. John , and S. Krishnan , \" NBTI impact on transistor and circuit: Models, mechanisms and scaling effects,\" IEEE International Electronic Devices Meeting , pp. 14.5.1 -- 14.5.4 , 2003 . A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, \"NBTI impact on transistor and circuit: Models, mechanisms and scaling effects,\" IEEE International Electronic Devices Meeting, pp. 14.5.1--14.5.4, 2003."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233601"},{"key":"e_1_3_2_1_6_1","first-page":"189","article-title":"Predictive modeling of the NBTI effect for reliable design","author":"Bhardwaj S.","year":"2006","unstructured":"S. Bhardwaj , W. Wang , R. Vattikonda , Y. Cao , and S. Vrudhula , \" Predictive modeling of the NBTI effect for reliable design ,\" Proceedings of the IEEE Custom Integrated Circuits Conference , pp. 189 -- 192 , 2006 . S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, \"Predictive modeling of the NBTI effect for reliable design,\" Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 189--192, 2006.","journal-title":"Proceedings of the IEEE Custom Integrated Circuits Conference"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2009.2028578"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1326073.1326227"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703295"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488856"},{"key":"e_1_3_2_1_11_1","volume-title":"Atomistic approach to variability of bias temperature instability in circuit simulations,\" Proceedings of the IEEE International Reliability Physics Symposium","author":"Kaczer B.","year":"2011","unstructured":"B. Kaczer , S. Mahato , V. V. de Almeida Camargo , M. Toledano-Luque , P. J. Roussel , T. Grasser , F. Catthoor , P. Dobrovolny , P. Zuber , G. Wirth , and G. Groeseneken , \" Atomistic approach to variability of bias temperature instability in circuit simulations,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. XT.3.1--XT.3.5, 2011 . B. Kaczer, S. Mahato, V. V. de Almeida Camargo, M. Toledano-Luque, P. J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth, and G. Groeseneken, \"Atomistic approach to variability of bias temperature instability in circuit simulations,\" Proceedings of the IEEE International Reliability Physics Symposium, pp. XT.3.1--XT.3.5, 2011."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228388"},{"key":"e_1_3_2_1_13_1","first-page":"6A","volume-title":"A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery,\" Proceedings of the IEEE International Reliability Physics Symposium","author":"Mahapatra S.","unstructured":"S. Mahapatra , A. E. Islam , S. Deora , V. D. Maheta , K. Joshi , A. Jain , and M. A. Alam , \" A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. 6A .3.1--6A.3.10, 2011. S. Mahapatra, A. E. Islam, S. Deora, V. D. Maheta, K. Joshi, A. Jain, and M. A. Alam, \"A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery,\" Proceedings of the IEEE International Reliability Physics Symposium, pp. 6A.3.1--6A.3.10, 2011."},{"key":"e_1_3_2_1_14_1","volume-title":"Understanding the impact of transistor-level BTI variability,\" Proceedings of the IEEE International Reliability Physics Symposium","author":"Fang J.","year":"2012","unstructured":"J. Fang and S. S. Sapatnekar , \" Understanding the impact of transistor-level BTI variability,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. CR2.1--CR2.6, 2012 . J. Fang and S. S. Sapatnekar, \"Understanding the impact of transistor-level BTI variability,\" Proceedings of the IEEE International Reliability Physics Symposium, pp. CR2.1--CR2.6, 2012."},{"key":"e_1_3_2_1_15_1","volume-title":"Hot-Carrier Effects in MOS Devices","author":"Takeda E.","year":"1995","unstructured":"E. Takeda , C. Y. Yang , and A. Miura-Hamada . Hot-Carrier Effects in MOS Devices . Academic Press , New York, NY , 1995 . E. Takeda, C. Y. Yang, and A. Miura-Hamada. Hot-Carrier Effects in MOS Devices. Academic Press, New York, NY, 1995."},{"issue":"9","key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","first-page":"1116","DOI":"10.1109\/T-ED.1984.21674","article-title":"Lucky-electron model of channel electron injection in MOSFET's","volume":"31","author":"Tam S.","year":"1984","unstructured":"S. Tam , P.-K. Ko , and C. Hu . \" Lucky-electron model of channel electron injection in MOSFET's ,\" IEEE Transactions on Electron Devices , D-31 ( 9 ), pp. 1116 -- 1125 , September 1984 . S. Tam, P.-K. Ko, and C. Hu. \"Lucky-electron model of channel electron injection in MOSFET's,\" IEEE Transactions on Electron Devices, D-31(9), pp. 1116--1125, September 1984.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.860560"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.901180"},{"key":"e_1_3_2_1_19_1","first-page":"531","article-title":"Hot-carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature","author":"Bravaix A.","year":"2009","unstructured":"A. Bravaix , C. Guerin , V. Huard , D. Roy , J. M. Roux , and E. Vincent , \" Hot-carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature ,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. 531 -- 548 , 2009 . A. Bravaix, C. Guerin, V. Huard, D. Roy, J. M. Roux, and E. Vincent, \"Hot-carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature,\" Proceedings of the IEEE International Reliability Physics Symposium, pp. 531--548, 2009.","journal-title":"Proceedings of the IEEE International Reliability Physics Symposium"},{"key":"e_1_3_2_1_20_1","first-page":"3","article-title":"Aging analysis of circuit timing considering NBTI and HCI","author":"Lorenz D.","year":"2009","unstructured":"D. Lorenz , G. Georgakos , and U. Schlichtmann , \" Aging analysis of circuit timing considering NBTI and HCI ,\" Proceedings of the IEEE International On-Line Testing Symposium , pp. 3 -- 8 , 2009 . D. Lorenz, G. Georgakos, and U. Schlichtmann, \"Aging analysis of circuit timing considering NBTI and HCI,\" Proceedings of the IEEE International On-Line Testing Symposium, pp. 3--8, 2009.","journal-title":"Proceedings of the IEEE International On-Line Testing Symposium"},{"key":"e_1_3_2_1_21_1","first-page":"591","volume-title":"The impact of hot carriers on timing in large circuits,\" Proceedings of the Asia-South Pacific Design Automation Conference","author":"Fang J.","year":"2012","unstructured":"J. Fang and S. S. Sapatnekar , The impact of hot carriers on timing in large circuits,\" Proceedings of the Asia-South Pacific Design Automation Conference , pp. 591 -- 596 , 2012 . J. Fang and S. S. Sapatnekar, The impact of hot carriers on timing in large circuits,\" Proceedings of the Asia-South Pacific Design Automation Conference, pp. 591--596, 2012."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/7298.946459"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.371590"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0287"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2119500"},{"key":"e_1_3_2_1_26_1","first-page":"698","article-title":"A statistical approach for full-chip gate-oxide reliability analysis","author":"Chopra K.","year":"2010","unstructured":"K. Chopra , C. Zhuo , D. Blaauw , and D. Sylvester , \" A statistical approach for full-chip gate-oxide reliability analysis ,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design , pp. 698 -- 705 , 2010 . K. Chopra, C. Zhuo, D. Blaauw, and D. Sylvester, \"A statistical approach for full-chip gate-oxide reliability analysis,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design, pp. 698--705, 2010.","journal-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_27_1","first-page":"638","article-title":"Scalable methods for the analysis and optimization of gate oxide breakdown","author":"Fang J.","year":"2010","unstructured":"J. Fang and S. S. Sapatnekar , \" Scalable methods for the analysis and optimization of gate oxide breakdown ,\" Proceedings of the International Symposium on Quality Electronic Design , pp. 638 -- 645 , 2010 . J. Fang and S. S. Sapatnekar, \"Scalable methods for the analysis and optimization of gate oxide breakdown,\" Proceedings of the International Symposium on Quality Electronic Design, pp. 638--645, 2010.","journal-title":"Proceedings of the International Symposium on Quality Electronic Design"},{"key":"e_1_3_2_1_28_1","first-page":"689","article-title":"Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability","author":"Fang J.","year":"2011","unstructured":"J. Fang and S. S. Sapatnekar , \" Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability ,\" Proceedings of the Asia-South Pacific Design Automation Conference , pp. 689 -- 694 , 2011 . J. Fang and S. S. Sapatnekar, \"Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability,\" Proceedings of the Asia-South Pacific Design Automation Conference, pp. 689--694, 2011.","journal-title":"Proceedings of the Asia-South Pacific Design Automation Conference"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1969.7340"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1971.8447"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.1993.283282"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.805728"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.322842"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123017"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855941"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853507"},{"key":"e_1_3_2_1_37_1","first-page":"571","article-title":"Variation-aware electromigration analysis of power\/ground networks","author":"Li D.","year":"2011","unstructured":"D. Li and M. Marek-Sadowska , \" Variation-aware electromigration analysis of power\/ground networks ,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design , pp. 571 -- 576 , 2011 . D. Li and M. Marek-Sadowska, \"Variation-aware electromigration analysis of power\/ground networks,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design, pp. 571--576, 2011.","journal-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_38_1","first-page":"682","article-title":"Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV)","author":"Karmarkar A.","year":"2009","unstructured":"A. Karmarkar , X. Xu , and V. Moroz , \" Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV) ,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. 682 -- 687 , 2009 . A. Karmarkar, X. Xu, and V. Moroz, \"Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV),\" Proceedings of the IEEE International Reliability Physics Symposium, pp. 682--687, 2009.","journal-title":"Proceedings of the IEEE International Reliability Physics Symposium"},{"key":"e_1_3_2_1_39_1","first-page":"3D","volume-title":"Thermomechanical reliability of through-silicon vias in 3D interconnects,\" Proceedings of the IEEE International Reliability Physics Symposium","author":"Lu K.-H.","unstructured":"K.-H. Lu , S.-K. Ryu , J.-H. Im , R. Huang , and P. S. Ho , \" Thermomechanical reliability of through-silicon vias in 3D interconnects,\" Proceedings of the IEEE International Reliability Physics Symposium , pp. 3D .1.1--3D.1.7, 2011. K.-H. Lu, S.-K. Ryu, J.-H. Im, R. Huang, and P. S. Ho, \"Thermomechanical reliability of through-silicon vias in 3D interconnects,\" Proceedings of the IEEE International Reliability Physics Symposium, pp. 3D.1.1--3D.1.7, 2011."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2010.2068572"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1982.20659"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837476"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024767"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228419"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429450"},{"key":"e_1_3_2_1_46_1","first-page":"563","article-title":"Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC","author":"Jung M.","year":"2011","unstructured":"M. Jung , X. Liu , S. Sitaraman , D. Z. Pan and S. K. Lim , \" Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC ,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design , pp. 563 -- 570 , 2011 . M. Jung, X. Liu, S. Sitaraman, D. Z. Pan and S. K. Lim, \"Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design, pp. 563--570, 2011.","journal-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_47_1","first-page":"555","article-title":"Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs","author":"Pathak M.","year":"2011","unstructured":"M. Pathak , J. Pak , D. Z. Pan , and S. K. Lim , \" Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs ,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design , pp. 555 -- 562 , 2011 . M. Pathak, J. Pak, D. Z. Pan, and S. K. Lim, \"Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs,\" Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design, pp. 555--562, 2011.","journal-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.73"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.37"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.32"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.30"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164957"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278574"},{"key":"e_1_3_2_1_54_1","first-page":"284","article-title":"Adaptive techniques for overcoming performance degradation due to aging in digital circuits","author":"Kumar S. V.","year":"2009","unstructured":"S. V. Kumar , C. H. Kim , and S. S. Sapatnekar , \" Adaptive techniques for overcoming performance degradation due to aging in digital circuits ,\" Proceedings of the Asia-South Pacific Design Automation Conference , pp. 284 -- 289 , 2009 . S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, \"Adaptive techniques for overcoming performance degradation due to aging in digital circuits,\" Proceedings of the Asia-South Pacific Design Automation Conference, pp. 284--289, 2009.","journal-title":"Proceedings of the Asia-South Pacific Design Automation Conference"},{"key":"e_1_3_2_1_55_1","first-page":"586","article-title":"Optimized self-tuning for circuit aging","author":"Mintarno E.","year":"2010","unstructured":"E. Mintarno , J. Skaf , R. Zheng , J. Velamala , Y. Cao , S. Boyd , R. W. Dutton , and S. Mitra , \" Optimized self-tuning for circuit aging ,\" Proceedings of Design, Automation and Test in Europe , pp. 586 -- 591 , 2010 . E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and S. Mitra, \"Optimized self-tuning for circuit aging,\" Proceedings of Design, Automation and Test in Europe, pp. 586--591, 2010.","journal-title":"Proceedings of Design, Automation and Test in Europe"},{"key":"e_1_3_2_1_56_1","first-page":"492","article-title":"Dick, \"Scheduled voltage scaling for increasing lifetime in the presence of NBTI","author":"Zhang L.","year":"2009","unstructured":"L. Zhang and Robert P . Dick, \"Scheduled voltage scaling for increasing lifetime in the presence of NBTI ,\" Proceedings of the Asia-South Pacific Design Automation Conference , pp. 492 -- 497 , 2009 . L. Zhang and Robert P. Dick, \"Scheduled voltage scaling for increasing lifetime in the presence of NBTI,\" Proceedings of the Asia-South Pacific Design Automation Conference, pp. 492--497, 2009.","journal-title":"Proceedings of the Asia-South Pacific Design Automation Conference"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669169"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006725"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.114"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917502"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040125"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.04.024"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2163894"},{"key":"e_1_3_2_1_64_1","first-page":"1","article-title":"Optimized circuit failure prediction for aging: Practicality and promise","author":"Agarwal M.","year":"2008","unstructured":"M. Agarwal , V. Balakrishnan , A. Bhuyan , K. Kim , B. C. Paul , W. Wang , B. Yang , Y. Cao , and S. Mitra , \" Optimized circuit failure prediction for aging: Practicality and promise ,\" Proceedings of the International Test Conference , pp. 1 -- 10 , 2008 . M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, B. C. Paul, W. Wang, B. Yang, Y. Cao, and S. Mitra, \"Optimized circuit failure prediction for aging: Practicality and promise,\" Proceedings of the International Test Conference, pp. 1--10, 2008.","journal-title":"Proceedings of the International Test Conference"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403590"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.56"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_15"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1870109.1870112"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2188457"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.5555\/2016802.2016840"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771785"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810264"},{"key":"e_1_3_2_1_73_1","first-page":"148","article-title":"Minimization of NBTI performance degradation using internal node control","author":"Bild D. R.","year":"2009","unstructured":"D. R. Bild , G. E. Bok , and R. P. Dick , \" Minimization of NBTI performance degradation using internal node control ,\" Proceedings of Design, Automation and Test in Europe , pp. 148 -- 153 , 2009 . D. R. Bild, G. E. Bok, and R. P. Dick, \"Minimization of NBTI performance degradation using internal node control,\" Proceedings of Design, Automation and Test in Europe, pp. 148--153, 2009.","journal-title":"Proceedings of Design, Automation and Test in Europe"},{"key":"e_1_3_2_1_74_1","first-page":"218","article-title":"NBTI Mitigation by Optimized NOP Assignment and Insertion","author":"Firouzi F.","year":"2012","unstructured":"F. Firouzi , S. Kiamehr , and M. B. Tahoori , \" NBTI Mitigation by Optimized NOP Assignment and Insertion ,\" Proceedings of Design, Automation and Test in Europe , pp. 218 -- 223 , 2012 . F. Firouzi, S. Kiamehr, and M. B. Tahoori, \"NBTI Mitigation by Optimized NOP Assignment and Insertion,\" Proceedings of Design, Automation and Test in Europe, pp. 218--223, 2012.","journal-title":"Proceedings of Design, Automation and Test in Europe"}],"event":{"name":"ICCAD '12: The International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"],"location":"San Jose California","acronym":"ICCAD '12"},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429431","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2429384.2429431","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:26Z","timestamp":1750235726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429431"}},"subtitle":["from physics to architectures"],"short-title":[],"issued":{"date-parts":[[2012,11,5]]},"references-count":74,"alternative-id":["10.1145\/2429384.2429431","10.1145\/2429384"],"URL":"https:\/\/doi.org\/10.1145\/2429384.2429431","relation":{},"subject":[],"published":{"date-parts":[[2012,11,5]]},"assertion":[{"value":"2012-11-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}