{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:35:52Z","timestamp":1773246952146,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,11,5]],"date-time":"2012-11-05T00:00:00Z","timestamp":1352073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["6.11E+15"],"award-info":[{"award-number":["6.11E+15"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,11,5]]},"DOI":"10.1145\/2429384.2429513","type":"proceedings-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:29:29Z","timestamp":1358868569000},"page":"597-604","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["Lazy man's logic synthesis"],"prefix":"10.1145","author":[{"given":"Wenlong","family":"Yang","sequence":"first","affiliation":[{"name":"Fudan University, Shanghai, China"}]},{"given":"Lingli","family":"Wang","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[{"name":"University of California, Berkeley"}]}],"member":"320","published-online":{"date-parts":[[2012,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065681"},{"key":"e_1_3_2_1_2_1","unstructured":"Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. http:\/\/www-cad.eecs.berkeley.edu\/~alanmi\/abc  Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification . http:\/\/www-cad.eecs.berkeley.edu\/~alanmi\/abc"},{"key":"e_1_3_2_1_3_1","first-page":"78","volume-title":"Proc. ICCAD '97","author":"Bertacco V.","unstructured":"V. Bertacco and M. Damiani . \" The disjunctive decomposition of logic functions \". Proc. ICCAD '97 , pp. 78 -- 82 . V. Bertacco and M. Damiani. \"The disjunctive decomposition of logic functions\". Proc. ICCAD '97, pp. 78--82."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382541"},{"key":"e_1_3_2_1_5_1","first-page":"29","volume-title":"ISCAS '82","author":"Brayton R.","unstructured":"R. Brayton and C. McMullen , \" The decomposition and factorization of Boolean expressions,\" Proc . ISCAS '82 , pp. 29 -- 54 . R. Brayton and C. McMullen, \"The decomposition and factorization of Boolean expressions,\" Proc. ISCAS '82, pp. 29--54."},{"key":"e_1_3_2_1_6_1","volume-title":"Proc. IEEE","volume":"78","author":"Brayton R.","year":"1990","unstructured":"R. Brayton , G. Hachtel , A. Sangiovanni-Vincentelli , \"Multilevel logic synthesis\" , Proc. IEEE , Vol. 78 , Feb. 1990 . R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, \"Multilevel logic synthesis\", Proc. IEEE, Vol. 78, Feb. 1990."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"e_1_3_2_1_8_1","first-page":"1929","volume-title":"ISCAS '89","author":"Brglez F.","unstructured":"F. Brglez , D. Bryan , and K. Kozminski , \" Combinational profiles of sequential benchmark circuits,\" Proc . ISCAS '89 , pp. 1929 -- 1934 . F. Brglez, D. Bryan, and K. Kozminski, \"Combinational profiles of sequential benchmark circuits,\" Proc. ISCAS '89, pp. 1929--1934."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1131481.1131780"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"e_1_3_2_1_11_1","unstructured":"ITC '99 Benchmarks. http:\/\/www.cad.polito.it\/tools\/itc99.html  ITC '99 Benchmarks. http:\/\/www.cad.polito.it\/tools\/itc99.html"},{"key":"e_1_3_2_1_12_1","first-page":"147","volume-title":"Proc. IWLS'10","author":"Kennings A.","unstructured":"A. Kennings , A. Mishchenko , K. Vorwerk , V. Pevzner , and A. Kundu , \" Generating efficient libraries for use in FPGA resynthesis algorithms \". Proc. IWLS'10 , pp. 147 -- 154 . A. Kennings, A. Mishchenko, K. Vorwerk, V. Pevzner, and A. Kundu, \"Generating efficient libraries for use in FPGA resynthesis algorithms\". Proc. IWLS'10, pp. 147--154."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"key":"e_1_3_2_1_14_1","volume-title":"Proc. IWLS'11","author":"Li N.","unstructured":"N. Li and E. Dubrova , \" AIG rewriting using 5-input cuts \", Proc. IWLS'11 . N. Li and E. Dubrova, \"AIG rewriting using 5-input cuts\", Proc. IWLS'11."},{"key":"e_1_3_2_1_15_1","first-page":"6","article-title":"Fast generation of prime-irredundant covers from binary decision diagrams","volume":"76","author":"Minato S.","year":"1993","unstructured":"S. Minato : \" Fast generation of prime-irredundant covers from binary decision diagrams ,\" IEICE Trans. Fundamentals , Vol. E76 -A, No. 6 , pp. 967--973, June 1993 . S. Minato: \"Fast generation of prime-irredundant covers from binary decision diagrams,\" IEICE Trans. Fundamentals, Vol. E76-A, No. 6, pp. 967--973, June 1993.","journal-title":"IEICE Trans. Fundamentals"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378353"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233679"},{"key":"e_1_3_2_1_19_1","first-page":"15","volume-title":"Proc. IWLS '06","author":"Mishchenko A.","unstructured":"A. Mishchenko and R. K. Brayton , \" Scalable logic synthesis using a simple circuit structure \", Proc. IWLS '06 , pp. 15 -- 22 . A. Mishchenko and R. K. Brayton, \"Scalable logic synthesis using a simple circuit structure\", Proc. IWLS '06, pp. 15--22."},{"key":"e_1_3_2_1_20_1","first-page":"354","volume-title":"Proc. ICCAD '07","author":"Mishchenko A.","unstructured":"A. Mishchenko , S. Cho , S. Chatterjee , R. Brayton , \"Combinational and sequential mapping with priority cuts \", Proc. ICCAD '07 , pp. 354 -- 361 . A. Mishchenko, S. Cho, S. Chatterjee, R. Brayton, \"Combinational and sequential mapping with priority cuts\", Proc. ICCAD '07, pp. 354--361."},{"key":"e_1_3_2_1_21_1","first-page":"375","volume-title":"Proc. ICCAD'11","author":"Mishchenko A.","unstructured":"A. Mishchenko , R. Brayton , S. Jang , and V. Kravets , \" Delay optimization using SOP balancing \", Proc. ICCAD'11 , pp. 375 -- 382 . A. Mishchenko, R. Brayton, S. Jang, and V. Kravets, \"Delay optimization using SOP balancing\", Proc. ICCAD'11, pp. 375--382."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"e_1_3_2_1_23_1","first-page":"230","volume-title":"Proc. IWLS '07","author":"Pistorius J.","unstructured":"J. Pistorius , M. Hutton , A. Mishchenko , and R. Brayton . \" Benchmarking method and designs targeting logic synthesis for FPGAs \", Proc. IWLS '07 , pp. 230 -- 237 . J. Pistorius, M. Hutton, A. Mishchenko, and R. Brayton. \"Benchmarking method and designs targeting logic synthesis for FPGAs\", Proc. IWLS '07, pp. 230--237."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.137523"},{"key":"e_1_3_2_1_25_1","volume-title":"Proc. DATE'12","author":"Ray S.","unstructured":"S. Ray , A. Mishchenko , N. Een , R. Brayton , S. Jang , and C. Chen , \" Mapping into LUT structures \", Proc. DATE'12 . S. Ray, A. Mishchenko, N. Een, R. Brayton, S. Jang, and C. Chen, \"Mapping into LUT structures\", Proc. DATE'12."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013899"},{"key":"e_1_3_2_1_28_1","volume-title":"Report","author":"Yang S.","year":"1991","unstructured":"S. Yang . \"Logic synthesis and optimization benchmarks\". Version 3.0. Tech. Report . Microelectronics Center of North Carolina , 1991 . S. Yang. \"Logic synthesis and optimization benchmarks\". Version 3.0. Tech. Report. Microelectronics Center of North Carolina, 1991."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20030575"},{"key":"e_1_3_2_1_30_1","first-page":"746","volume-title":"Proc. DAC'05","author":"Wu D.","unstructured":"D. Wu and J. Zhu , \" FBDD: a folded logic synthesis system \", Proc. DAC'05 , pp. 746 -- 751 . D. Wu and J. Zhu, \"FBDD: a folded logic synthesis system\", Proc. DAC'05, pp. 746--751."},{"key":"e_1_3_2_1_31_1","unstructured":"https:\/\/skydrive.live.com\/redir.aspx?cid=76d4b8991df82cf3&resid=76D4B8991DF82CF3!152&parid=roo  https:\/\/skydrive.live.com\/redir.aspx?cid=76d4b8991df82cf3&resid=76D4B8991DF82CF3!152&parid=roo"}],"event":{"name":"ICCAD '12: The International Conference on Computer-Aided Design","location":"San Jose California","acronym":"ICCAD '12","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429513","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2429384.2429513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:26Z","timestamp":1750235726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429513"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11,5]]},"references-count":30,"alternative-id":["10.1145\/2429384.2429513","10.1145\/2429384"],"URL":"https:\/\/doi.org\/10.1145\/2429384.2429513","relation":{},"subject":[],"published":{"date-parts":[[2012,11,5]]},"assertion":[{"value":"2012-11-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}