{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T13:55:09Z","timestamp":1770040509097,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,11,5]],"date-time":"2012-11-05T00:00:00Z","timestamp":1352073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["NSC 98-2221-E-006-156-MY3NSC 101-2220-E-006-006"],"award-info":[{"award-number":["NSC 98-2221-E-006-156-MY3NSC 101-2220-E-006-006"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,11,5]]},"DOI":"10.1145\/2429384.2429520","type":"proceedings-article","created":{"date-parts":[[2013,1,22]],"date-time":"2013-01-22T15:29:29Z","timestamp":1358868569000},"page":"635-642","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits"],"prefix":"10.1145","author":[{"given":"Cheng-Wu","family":"Lin","sequence":"first","affiliation":[{"name":"National Cheng Kung University, Tainan, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Lin","family":"Lee","sequence":"additional","affiliation":[{"name":"National Cheng Kung University, Tainan, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jai-Ming","family":"Lin","sequence":"additional","affiliation":[{"name":"National Cheng Kung University, Tainan, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soon-Jyh","family":"Chang","sequence":"additional","affiliation":[{"name":"National Cheng Kung University, Tainan, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,11,5]]},"reference":[{"issue":"6","key":"e_1_3_2_1_1_1","first-page":"1085","article-title":"Biquad alternatives for high-frequency switched-capacitor filters","volume":"20","author":"Ribner D. B.","year":"1985","unstructured":"D. B. Ribner and M. A. Copeland , \" Biquad alternatives for high-frequency switched-capacitor filters ,\" IEEE JSSC , vol. 20 , no. 6 , pp. 1085 -- 1095 , Dec. 1985 . D. B. Ribner and M. A. Copeland, \"Biquad alternatives for high-frequency switched-capacitor filters,\" IEEE JSSC, vol. 20, no. 6, pp. 1085--1095, Dec. 1985.","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052250"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.284714"},{"key":"e_1_3_2_1_4_1","volume-title":"The Art of Analog Layout","author":"Hastings A.","year":"2006","unstructured":"A. Hastings , The Art of Analog Layout , 2 nd Ed., Prentice Hall , 2006 . A. Hastings, The Art of Analog Layout, 2nd Ed., Prentice Hall, 2006.","edition":"2"},{"key":"e_1_3_2_1_5_1","first-page":"300","volume-title":"IEEE MIXDES","author":"Haenzsche S.","year":"2010","unstructured":"S. Haenzsche , S. Henker , and R. Schuffny , \" Modelling of capacitor mismatch and non-linearity effects in charge redistribution SAR ADCs,\" in Proc . IEEE MIXDES , 2010 , pp. 300 -- 305 . S. Haenzsche, S. Henker, and R. Schuffny, \"Modelling of capacitor mismatch and non-linearity effects in charge redistribution SAR ADCs,\" in Proc. IEEE MIXDES, 2010, pp. 300--305."},{"issue":"7","key":"e_1_3_2_1_6_1","first-page":"585","article-title":"Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays","volume":"47","author":"Cong Y.","year":"2000","unstructured":"Y. Cong and R. L. Geiger , \" Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays ,\" IEEE TCAS II , vol. 47 , no. 7 , pp. 585 -- 595 , Jul. 2000 . Y. Cong and R. L. Geiger, \"Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays,\" IEEE TCAS II, vol. 47, no. 7, pp. 585--595, Jul. 2000.","journal-title":"IEEE TCAS II"},{"key":"e_1_3_2_1_7_1","first-page":"400","volume-title":"IEEE ISCAS","author":"Shi C.","year":"2001","unstructured":"C. Shi , J. Wilson , and M. Ismail , \" Design techniques for improving intrinsic accuracy of resistor string DAC's,\" in Proc . IEEE ISCAS , 2001 , pp. 400 -- 403 . C. Shi, J. Wilson, and M. Ismail, \"Design techniques for improving intrinsic accuracy of resistor string DAC's,\" in Proc. IEEE ISCAS, 2001, pp. 400--403."},{"key":"e_1_3_2_1_8_1","first-page":"272","article-title":"Measurement and modeling of MOS transistor current mismatch in analog IC's","author":"Felt E.","year":"1994","unstructured":"E. Felt , A. Narayan , and A. Sangiovanni-Vincentelli , \" Measurement and modeling of MOS transistor current mismatch in analog IC's ,\" in Proc. IEEE\/ACM ICCAD , 1994 , pp. 272 -- 277 . E. Felt, A. Narayan, and A. Sangiovanni-Vincentelli, \"Measurement and modeling of MOS transistor current mismatch in analog IC's,\" in Proc. IEEE\/ACM ICCAD, 1994, pp. 272--277.","journal-title":"Proc. IEEE\/ACM ICCAD"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"issue":"12","key":"e_1_3_2_1_10_1","first-page":"1708","article-title":"Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, \"A 14-bit intrinsic accuracy Q2 random walk CMOS DAC","volume":"34","author":"G. A.","year":"1999","unstructured":"G. A. M . Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, \"A 14-bit intrinsic accuracy Q2 random walk CMOS DAC ,\" IEEE JSSC , vol. 34 , no. 12 , pp. 1708 -- 1718 , Dec. 1999 . G. A. M. Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, \"A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,\" IEEE JSSC, vol. 34, no. 12, pp. 1708--1718, Dec. 1999.","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.735536"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.75066"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/66.572070"},{"issue":"8","key":"e_1_3_2_1_14_1","first-page":"502","article-title":"A switching sequence for linear gradient error compensation in the DAC design","volume":"58","author":"Kuo K.-C.","year":"2011","unstructured":"K.-C. Kuo and C.-W. Wu , \" A switching sequence for linear gradient error compensation in the DAC design ,\" IEEE TCAS II , vol. 58 , no. 8 , pp. 502 -- 506 , Aug. 2011 . K.-C. Kuo and C.-W. Wu, \"A switching sequence for linear gradient error compensation in the DAC design,\" IEEE TCAS II, vol. 58, no. 8, pp. 502--506, Aug. 2011.","journal-title":"IEEE TCAS II"},{"issue":"12","key":"e_1_3_2_1_15_1","first-page":"1002","article-title":"Gradient error cancellation and quadratic error reduction in unary and binary D\/A converters","volume":"50","author":"Vadipour M.","year":"2003","unstructured":"M. Vadipour , \" Gradient error cancellation and quadratic error reduction in unary and binary D\/A converters ,\" IEEE TCAS II , vol. 50 , no. 12 , pp. 1002 -- 1007 , Dec. 2003 . M. Vadipour, \"Gradient error cancellation and quadratic error reduction in unary and binary D\/A converters,\" IEEE TCAS II, vol. 50, no. 12, pp. 1002--1007, Dec. 2003.","journal-title":"IEEE TCAS II"},{"key":"e_1_3_2_1_16_1","first-page":"576","article-title":"Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio","author":"Sayed D.","year":"2002","unstructured":"D. Sayed and M. Dessouky , \" Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio ,\" in Proc. ACM\/IEEE DATE , 2002 , pp. 576 -- 580 . D. Sayed and M. Dessouky, \"Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio,\" in Proc. ACM\/IEEE DATE, 2002, pp. 576--580.","journal-title":"Proc. ACM\/IEEE DATE"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"e_1_3_2_1_18_1","first-page":"579","article-title":"Analog placement with common centroid constraints","author":"Ma Q.","year":"2007","unstructured":"Q. Ma , E. F. Y. Young , and K. P. Pun , \" Analog placement with common centroid constraints ,\" in Proc. IEEE\/ACM ICCAD , 2007 , pp. 579 -- 585 . Q. Ma, E. F. Y. Young, and K. P. Pun, \"Analog placement with common centroid constraints,\" in Proc. IEEE\/ACM ICCAD, 2007, pp. 579--585.","journal-title":"Proc. IEEE\/ACM ICCAD"},{"key":"e_1_3_2_1_19_1","first-page":"306","article-title":"Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions","author":"Strasser M.","year":"2008","unstructured":"M. Strasser , M. Eick , H. Graeb , U. Schlichtmann , and F. M. Johannes , \" Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions ,\" in Proc. IEEE\/ACM ICCAD , 2008 , pp. 306 -- 313 . M. Strasser, M. Eick, H. Graeb, U. Schlichtmann, and F. M. Johannes, \"Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions,\" in Proc. IEEE\/ACM ICCAD, 2008, pp. 306--313.","journal-title":"Proc. IEEE\/ACM ICCAD"},{"key":"e_1_3_2_1_20_1","first-page":"353","article-title":"Analog placement with common centroid and 1-D symmetry sonstraints","author":"Xiao L.","year":"2009","unstructured":"L. Xiao and E. F. Y. Young , \" Analog placement with common centroid and 1-D symmetry sonstraints ,\" in Proc. ACM\/IEEE ASP-DAC , 2009 , pp. 353 -- 360 . L. Xiao and E. F. Y. Young, \"Analog placement with common centroid and 1-D symmetry sonstraints,\" in Proc. ACM\/IEEE ASP-DAC, 2009, pp. 353--360.","journal-title":"Proc. ACM\/IEEE ASP-DAC"},{"key":"e_1_3_2_1_21_1","first-page":"1739","volume-title":"IEEE ISCAS","author":"Soares C. F. T.","year":"2009","unstructured":"C. F. T. Soares and A. Petraglia , \" Automatic placement of identical unit capacitors to improve capacitance matching,\" in Proc . IEEE ISCAS , 2009 , pp. 1739 -- 1742 . C. F. T. Soares and A. Petraglia, \"Automatic placement of identical unit capacitors to improve capacitance matching,\" in Proc. IEEE ISCAS, 2009, pp. 1739--1742."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006139"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810290"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035587"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024847"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630064"},{"key":"e_1_3_2_1_27_1","first-page":"693","article-title":"Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer","volume":"6","author":"Naylor W. C.","year":"2001","unstructured":"W. C. Naylor , R. Donelly , and L. Sha , \" Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer ,\" U.S. Patent 6 301 693 , Oct. 9, 2001 . W. C. Naylor, R. Donelly, and L. Sha, \"Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,\" U.S. Patent 6 301 693, Oct. 9, 2001.","journal-title":"U.S. Patent"},{"key":"e_1_3_2_1_28_1","volume-title":"Linear and Nonlinear Programming","author":"Nash S. G.","year":"1996","unstructured":"S. G. Nash and A. Sofer , Linear and Nonlinear Programming , McGraw-Hill International Editions , 1996 . S. G. Nash and A. Sofer, Linear and Nonlinear Programming, McGraw-Hill International Editions, 1996."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","DOI":"10.1002\/9781118033340","volume-title":"An Introduction to Optimization","author":"Chong E. K. P.","year":"2008","unstructured":"E. K. P. Chong and S. H. Zak , An Introduction to Optimization , 3 rd Ed., Wiley-Interscience , 2008 . E. K. P. Chong and S. H. Zak, An Introduction to Optimization, 3rd Ed., Wiley-Interscience, 2008.","edition":"3"}],"event":{"name":"ICCAD '12: The International Conference on Computer-Aided Design","location":"San Jose California","acronym":"ICCAD '12","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429520","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2429384.2429520","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:26Z","timestamp":1750235726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2429384.2429520"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11,5]]},"references-count":29,"alternative-id":["10.1145\/2429384.2429520","10.1145\/2429384"],"URL":"https:\/\/doi.org\/10.1145\/2429384.2429520","relation":{},"subject":[],"published":{"date-parts":[[2012,11,5]]},"assertion":[{"value":"2012-11-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}