{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T23:45:24Z","timestamp":1771631124272,"version":"3.50.1"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"1s","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Australian Government's International Science Linkages Program"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3]]},"abstract":"<jats:p>A new architecture, QUKU, is proposed for implementing stream-based algorithms on FPGAs, which combines the advantages of FPGA and Coarse Grain Reconfigurable Arrays (CGRAs). QUKU consists of a dynamically reconfigurable, coarse-grain Processing Element (PE) array with an associated softcore processor providing system support. At a coarse-grain, the PE array can be reconfigured on a cycle-by-cycle basis to change the PE functionality similarly to that in a conventional CGRA. At a fine-grain, the whole FPGA can be reconfigured statically to implement a completely different PE array that serves the target application in a better way. Advantages of the fine-grain reconfiguration include individually customized PEs, adaptable numeric format support and customizable interconnect network. A prototype CAD tool framework is also developed which facilitates programming the QUKU architecture. An example application consisting of two different image detectors is implemented to demonstrate the advantages of QUKU. QUKU provides up to 140 times speedup and 40 times improvement in area-time product compared to an implementation running on an FPGA-based softcore. The area-time product for QUKU is around 16% lower than that of a custom circuit based implementation on the same FPGA. The per-PE customization provides an area-time saving of approximately 31% compared to a homogeneous 4 \u00d7 4 array of PEs for the same application. The experimental results demonstrate that a dual layered reconfigurable architecture provides significant potential benefits in terms of flexibility, area and processing efficiency over existing reconfigurable computing architectures for DSP.<\/jats:p>","DOI":"10.1145\/2435227.2435259","type":"journal-article","created":{"date-parts":[[2018,1,4]],"date-time":"2018-01-04T16:27:31Z","timestamp":1515083251000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["QUKU"],"prefix":"10.1145","volume":"12","author":[{"given":"Neil W.","family":"Bergmann","sequence":"first","affiliation":[{"name":"University of Queensland, Brisbane, Australia"}]},{"given":"Sunil K.","family":"Shukla","sequence":"additional","affiliation":[{"name":"IBM TJ Watson Research Center, Hawthorne, NY"}]},{"given":"J\u00fcrgen","family":"Becker","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Germany"}]}],"member":"320","published-online":{"date-parts":[[2013,3,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1002\/0471745790"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Euope (DATE'06)","author":"Ahn M.","unstructured":"Ahn , M. , Yoon , J. W. , Paek , Y. , Kim , Y. , Kiemb , M. , and Choi , K . 2006. A spatial mapping algorithm for heterogeneous coarse-grained recodigurable architechures . In Proceedings of the Conference on Design, Automation and Test in Euope (DATE'06) . European Design and Automation Association, Leuven, Belgium, 363--368. Ahn, M., Yoon, J. W., Paek, Y., Kim, Y., Kiemb, M., and Choi, K. 2006. A spatial mapping algorithm for heterogeneous coarse-grained recodigurable architechures. In Proceedings of the Conference on Design, Automation and Test in Euope (DATE'06). European Design and Automation Association, Leuven, Belgium, 363--368."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.29"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"e_1_2_1_6_1","unstructured":"Eto E. 2007. Difference-based partial reconfiguration. Xilinx Appli. Note. www.xilinx.com.  Eto E. 2007. Difference-based partial reconfiguration. Xilinx Appli. Note. www.xilinx.com."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508158"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. K. L. Pocek, J. M. Arnold, Eds., IEEE Computer Society","author":"Hauser J. R.","unstructured":"Hauser , J. R. and Wawrzynek , J . 1999. Garp: a MIPS processor with a reconfigurable coprocessor . In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. K. L. Pocek, J. M. Arnold, Eds., IEEE Computer Society , Los Alamitos, CA, 12--21. Hauser, J. R. and Wawrzynek, J. 1999. Garp: a MIPS processor with a reconfigurable coprocessor. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. K. L. Pocek, J. M. Arnold, Eds., IEEE Computer Society, Los Alamitos, CA, 12--21."},{"key":"e_1_2_1_9_1","volume-title":"Coarse-grained reconfigurable processors - flexibility meets efficiency","author":"Heysters P. M.","unstructured":"Heysters , P. M. 2002. Coarse-grained reconfigurable processors - flexibility meets efficiency . PhD Thesis University of Twente , The Netherlands . Heysters, P. M. 2002. Coarse-grained reconfigurable processors - flexibility meets efficiency. PhD Thesis University of Twente, The Netherlands."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/647928.739731"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0134-x"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008189221436"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/647929.740398"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_7"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850844"},{"key":"e_1_2_1_17_1","first-page":"157","article-title":"CRC -- Concepts and evaluation of processor-like reconfigurable architectures","volume":"49","author":"Oppold T.","year":"2007","unstructured":"Oppold , T. , Schweizer , T. , Filho , J. O. , Eisenhardt , S. , and Rosenthal , W. 2007 . CRC -- Concepts and evaluation of processor-like reconfigurable architectures . Inf. Technol. 49 , 3, 157 -- 164 . Oppold, T., Schweizer, T., Filho, J. O., Eisenhardt, S., and Rosenthal, W. 2007. CRC -- Concepts and evaluation of processor-like reconfigurable architectures. Inf. Technol. 49, 3, 157--164.","journal-title":"Inf. Technol."},{"key":"e_1_2_1_18_1","unstructured":"Recore Systems. 2007. Montium reconfigurable digital signal processing tile processor datasheet www.recoresystems.com.  Recore Systems. 2007. Montium reconfigurable digital signal processing tile processor datasheet www.recoresystems.com."},{"key":"e_1_2_1_19_1","unstructured":"Rosinge H.-P. 2004. Connecting customized IP to the MicroBlaze soft processor using the fast simplex link (FSL) Channel. Xilinx Appli. Note XAPP529. http:\/\/www.origin.xilinx.com\/support\/documentation\/application_notes\/xapp529.pdf.  Rosinge H.-P. 2004. Connecting customized IP to the MicroBlaze soft processor using the fast simplex link (FSL) Channel. Xilinx Appli. Note XAPP529. http:\/\/www.origin.xilinx.com\/support\/documentation\/application_notes\/xapp529.pdf."},{"key":"e_1_2_1_20_1","unstructured":"Shukla S. K. 2008. QUKU: A mixed grain dynamically reconfigurable architecture for high performance computing. PhD Thesis University of Queensland Brisbane Australia.  Shukla S. K. 2008. QUKU: A mixed grain dynamically reconfigurable architecture for high performance computing. PhD Thesis University of Queensland Brisbane Australia."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms T. Plaaks, Ed., CSREA Press","author":"Smit G. J. M.","unstructured":"Smit , G. J. M. , Guo , Y. , and Heysters , P. M . 2004. Overview of the tool-flow for the Montium processor tile , In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms T. Plaaks, Ed., CSREA Press , Irvine, CA, 45--51. Smit, G. J. M., Guo, Y., and Heysters, P. M. 2004. Overview of the tool-flow for the Montium processor tile, In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms T. Plaaks, Ed., CSREA Press, Irvine, CA, 45--51."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045086"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233647"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950436"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2007.361613"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/1496388"},{"key":"e_1_2_1_29_1","unstructured":"Xilinx. 2007. Microblaze Processor Reference Guide v7.1 www.xilinx.com.  Xilinx. 2007. Microblaze Processor Reference Guide v7.1 www.xilinx.com."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356988"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2435227.2435259","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2435227.2435259","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:56Z","timestamp":1750234736000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2435227.2435259"}},"subtitle":["A dual-layer reconfigurable architecture"],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":29,"journal-issue":{"issue":"1s","published-print":{"date-parts":[[2013,3]]}},"alternative-id":["10.1145\/2435227.2435259"],"URL":"https:\/\/doi.org\/10.1145\/2435227.2435259","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]},"assertion":[{"value":"2010-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-03-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}