{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:48:43Z","timestamp":1761648523672,"version":"3.41.0"},"reference-count":39,"publisher":"Association for Computing Machinery (ACM)","issue":"1s","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004895","name":"European Social Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004895","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["216415"],"award-info":[{"award-number":["216415"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004837","name":"Ministerio de Ciencia e Innovaci\u00f3n","doi-asserted-by":"publisher","award":["Juan de 1a Cierva JCI2009-05455"],"award-info":[{"award-number":["Juan de 1a Cierva JCI2009-05455"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3]]},"abstract":"<jats:p>Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated architectures such as IMA or AUTOSAR is limited by the fact that multicores do not guarantee a<jats:italic>time composable<\/jats:italic>behavior for the applications: the WCET of a task depends on inter-task interferences introduced by other tasks running simultaneously.<\/jats:p><jats:p>This article focuses on the off-chip memory system: the hardware shared resource with the highest impact on the WCET and hence the main impediment for the use of multicores in integrated architectures. We present an analytical model that computes the worst-case delay, also known as<jats:italic>Upper Bound Delay<\/jats:italic>(UBD), that a memory request can suffer due to memory interferences generated by other co-running tasks. By considering the UBD in the WCET analysis, the resulting WCET estimation is independent from the other tasks, hence ensuring the time composability property and enabling the use of multicores in integrated architectures. We propose a memory controller for hard real-time multicores compliant with the analytical model that implements extra hardware features to deal with refresh operations and interferences generated by co-running non hard real-time tasks.<\/jats:p>","DOI":"10.1145\/2435227.2435260","type":"journal-article","created":{"date-parts":[[2018,1,4]],"date-time":"2018-01-04T16:27:31Z","timestamp":1515083251000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["Timing effects of DDR memory systems in hard real-time multicore architectures"],"prefix":"10.1145","volume":"12","author":[{"given":"Marco","family":"Paolieri","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center (BSC), Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo","family":"Qui\u00f1ones","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Spanish National Research Council (IIIA-CSIC) and BSC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,3,29]]},"reference":[{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289877"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.167"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.33"},{"volume-title":"Specification 651: Design Guide for Integrated Modular Avionics. Aeronautical Radio","key":"e_1_2_1_5_1","unstructured":"ARINC. 1997. Specification 651: Design Guide for Integrated Modular Avionics. Aeronautical Radio , Inc . ARINC. 1997. Specification 651: Design Guide for Integrated Modular Avionics. Aeronautical Radio, Inc."},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"AUTOSAR. 2006. Technical overview V2.0.1. AUTOSAR. 2006. Technical overview V2.0.1.","DOI":"10.1049\/cp:20060681"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/827272.829144"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2010.23"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"volume-title":"Proceedings of ERTS.","author":"Cullmann C.","key":"e_1_2_1_10_1","unstructured":"Cullmann , C. , Ferdinand 1, C., Gebhard , G. , Grund , D. , Maiza , C. , Reineke , J. , Triquet , B. , and Wilhelm , R . 2010. Predictability considerations in the design of multi-core embedded systems . In Proceedings of ERTS. Cullmann, C., Ferdinand1, C., Gebhard, G., Grund, D., Maiza, C., Reineke, J., Triquet, B., and Wilhelm, R. 2010. Predictability considerations in the design of multi-core embedded systems. In Proceedings of ERTS."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023837"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455231"},{"key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","volume-title":"Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann.","author":"Jacob B.","year":"2008","unstructured":"Jacob , B. , Ng , S. W. , and Wang , D. T . 2008 . Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann. Jacob, B., Ng, S. W., and Wang, D. T. 2008. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann."},{"key":"e_1_2_1_15_1","unstructured":"JEDEC. 2008. DDR2 SDRAM Specification JEDEC Standard No. JESD79-2E. JEDEC. 2008. DDR2 SDRAM Specification JEDEC Standard No. JESD79-2E."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.846412"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450117"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/827271.829103"},{"key":"e_1_2_1_19_1","unstructured":"MERASA. 2007. EU-FP7 project. www.merasa.org. MERASA. 2007. EU-FP7 project. www.merasa.org."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2014005"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555764"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1871105"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380666"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1288940.1288962"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1814539.1814548"},{"volume-title":"Characterization of the EEMBC Benchmark Suite","author":"Poovey J.","key":"e_1_2_1_27_1","unstructured":"Poovey , J. 2007. Characterization of the EEMBC Benchmark Suite . North Carolina State University . Poovey, J. 2007. Characterization of the EEMBC Benchmark Suite. North Carolina State University."},{"key":"e_1_2_1_28_1","unstructured":"RapiTime. 2008. www.rapitasystems.com. RapiTime. 2008. www.rapitasystems.com."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.22"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.13"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1017753.1017798"},{"key":"e_1_2_1_34_1","doi-asserted-by":"crossref","unstructured":"Thiele L. and Wilhelm R. 2004. Design for time-predictability. In Design of Systems with Predictable Behaviour. Thiele L. and Wilhelm R. 2004. Design for time-predictability. In Design of Systems with Predictable Behaviour.","DOI":"10.1023\/B:TIME.0000045316.66276.6e"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSPIT.2005.1577063"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.78"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291044"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/QSIC.2005.49"},{"key":"e_1_2_1_40_1","doi-asserted-by":"crossref","unstructured":"Wolf W. 2007. High-Performance Embedded Computing. Morgan Kaufmann. Wolf W. 2007. High-Performance Embedded Computing. Morgan Kaufmann.","DOI":"10.1016\/B978-012369485-0\/50002-6"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2435227.2435260","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2435227.2435260","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T10:52:22Z","timestamp":1751194342000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2435227.2435260"}},"subtitle":["Issues and solutions"],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":39,"journal-issue":{"issue":"1s","published-print":{"date-parts":[[2013,3]]}},"alternative-id":["10.1145\/2435227.2435260"],"URL":"https:\/\/doi.org\/10.1145\/2435227.2435260","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2013,3]]},"assertion":[{"value":"2011-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-03-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}