{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T06:04:09Z","timestamp":1780466649348,"version":"3.54.1"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["NSC 97-2221-E-033-053-MY3"],"award-info":[{"award-number":["NSC 97-2221-E-033-053-MY3"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,3]]},"abstract":"<jats:p>In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities, leading to different delay degradations. If the degradation difference is not properly controlled, this clock skew may cause the circuit fails to function at some point later in time. Intuitively, the degradation difference can be eliminated, if we increase the active probability of the low-probability clock gates to ensure the clock gates at the same level always having the same active probability. However, this intuitive method may suffer from large power consumption overhead. In this article, we point out, by carefully planning the transistor-level clock signal propagation path, we can have many clock gates whose active probabilities do not affect the degradation difference. Based on that observation, we propose a critical-PMOS-aware clock tree design methodology to eliminate the degradation difference with minimum power consumption overhead. Benchmark data consistently show our approach achieves very good results in terms of both the NBTI-induced clock skew (i.e., the degradation difference) and the power consumption overhead.<\/jats:p>","DOI":"10.1145\/2442087.2442098","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Low-power anti-aging zero skew clock gating"],"prefix":"10.1145","volume":"18","author":[{"given":"Shih-Hsu","family":"Huang","sequence":"first","affiliation":[{"name":"Chung Yuan Christian University, Taiwan, R.O.C"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wen-Pin","family":"Tu","sequence":"additional","affiliation":[{"name":"Chung Yuan Christian University, Taiwan, R.O.C"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chia-Ming","family":"Chang","sequence":"additional","affiliation":[{"name":"Chung Yuan Christian University, Taiwan, R.O.C"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Song-Bin","family":"Pan","sequence":"additional","affiliation":[{"name":"Chung Yuan Christian University, Taiwan, R.O.C"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2013,4,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735056"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE\/ACM Conference and Exhibition on Design, Automation and Test in Europe. 296--299","author":"Chakraborty A."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391653"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204128"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297686"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1587\/elex.5.762"},{"key":"e_1_2_1_7_1","unstructured":"Cohn J. M. Neves J. L. P. C. and Zuchowski P. S. 2003. Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design. United States Patent No. 6651230.  Cohn J. M. Neves J. L. P. C. and Zuchowski P. S. 2003. Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design. United States Patent No. 6651230."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/293625.293628"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775989"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.924824"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313913"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE Asia and South Pacific Design Automation Conference. 480--485","author":"Huang S. H."},{"key":"e_1_2_1_15_1","first-page":"1651","article-title":"Synthesis of anti-aging gated clock designs","volume":"25","author":"Huang S. H.","year":"2009","journal-title":"J. Inf. Sci. Engin."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278574"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the IEEE International Symposium on Microarchitecture. 330--335","author":"Lee C."},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer Design. 217--223","author":"Mehta A. D."},{"key":"e_1_2_1_19_1","unstructured":"Micheli G. D. 1995. Synthesis and Optimization of Digital Circuits. Kluwer Academic Publishers.   Micheli G. D. 1995. Synthesis and Optimization of Digital Circuits. Kluwer Academic Publishers."},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the IEEE\/ACM Design Automation and Test in Europe. 692--697","author":"Oh J."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2005.852523"},{"key":"e_1_2_1_22_1","unstructured":"Rodgers R. S. and Evans S. T. 2004. Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load. United States Patent No. 6769104.  Rodgers R. S. and Evans S. T. 2004. Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load. United States Patent No. 6769104."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.205004"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442087.2442098","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2442087.2442098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:25Z","timestamp":1750235725000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442087.2442098"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":24,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2013,3]]}},"alternative-id":["10.1145\/2442087.2442098"],"URL":"https:\/\/doi.org\/10.1145\/2442087.2442098","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]},"assertion":[{"value":"2012-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-04-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}