{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:21:37Z","timestamp":1750306897909,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,3,10]],"date-time":"2013-03-10T00:00:00Z","timestamp":1362873600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Israel Ministry of Science and Technology","award":["Mar-96"],"award-info":[{"award-number":["Mar-96"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3,10]]},"abstract":"<jats:p>One of the main advantages of high-level synthesis (HLS) is the ability to synthesize circuits that can access multiple memory banks in parallel. Current HLS systems synthesize parallel memory references based on explicit array declarations in the source code. We consider the need to synthesize not only array references but also memory operations targeting pointers and dynamic data structures. This paper describes Automatic Memory Partitioning, a method for automatically synthesizing general data structures (arrays and pointers) into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. We present an algorithm for allocating memory segments into multiple memory banks. Experiments show significant improvements in performance while conserving the number of memory banks.<\/jats:p>","DOI":"10.1145\/2442116.2442118","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Using memory profile analysis for automatic synthesis of pointers code"],"prefix":"10.1145","volume":"12","author":[{"given":"Yosi","family":"Ben-Asher","sequence":"first","affiliation":[{"name":"Haifa University"}]},{"given":"Nadav","family":"Rotem","sequence":"additional","affiliation":[{"name":"Haifa University"}]}],"member":"320","published-online":{"date-parts":[[2013,4,8]]},"reference":[{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD). 276--279","author":"Ahmad I.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/110382.110385"},{"volume-title":"Proceedings of the IEEE System-on-Chip International Symposium (SoC). 1--4.","author":"Ben-Asher Y.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878989"},{"volume-title":"Proceedings of the IEEE System-on-Chip International Symposium (SoC'08)","author":"Ben-Asher Y.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"Cardoso J. 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